Hardware Address Generator for CNN Multi-Dimensional Data Access
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Solution Overview
Problem
Convolutional neural networks (CNNs) face high computational complexity due to the need for simultaneous access and manipulation of large, multi-dimensional data arrays, which is inefficient and energy-intensive, especially in deep learning applications where high-dimensional convolutions and extensive data operations are required.
Innovation Solution
A memory address generator is developed to efficiently access multi-dimensional data by generating addresses using a combination of iteration variables, convolutional strides, and bounds, utilizing MUL-ADD units to compute memory addresses for input, coefficient, and output data, allowing for pre-fetching and instant calculation, thereby improving data access and computation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional 'for' statements are used to generate iteration variables for multi-dimensional data access, then the programming approach is simple and widely supported, but the computational complexity and data access efficiency are poor
Solution Approach 1:
The patent replaces software-based iteration variable generation (using 'for' statements) with a dedicated hardware address generator that uses multiplication and addition circuits to compute memory addresses directly from iteration variables, substituting the mechanical/software process with an electronic/hardware solution to achieve faster data access
Solution Approach 2:
The address generator performs preliminary computation of memory addresses by pre-calculating the address arithmetic operations (multiplication and addition) before data access occurs, allowing the memory system to be prepared in advance and improving overall data retrieval efficiency
2Productivity
If hardware-based address generation with MUL-ADD units is implemented, then data access speed and computational efficiency are improved, but the device complexity increases
Solution Approach 1:
The address generator is designed as a universal module that can handle multiple data types and access patterns through a single unified architecture, where the same MUL-ADD units and iteration variable generator can service different memory access requirements without requiring separate dedicated circuits for each function
Solution Approach 2:
The patent implements nested iteration variables where inner iteration variables are multiplied by stride values and added to outer iteration variable contributions in a hierarchical nested structure, allowing complex multi-dimensional addressing to be built up from simpler nested components
3Adaptability or versatility
If multiple iteration variables are used to access multi-dimensional arrays, then comprehensive data coverage is achieved, but the computational complexity and energy consumption increase
Solution Approach 1:
The patent extracts the address calculation functionality from the main computational loop and places it in a dedicated address generator unit, separating the memory access computation from the data processing computation, which reduces the energy consumption of the overall system by optimizing the memory access path independently
Data Source
AI summary
A process for iterating through a multi-dimensional array has an iteration process and an address generation process. In one example of the invention an input address process, a coefficient address process, and an output address process generate addresses for a convolutional neural network (CNN. Each of the input address process, coefficient address process, and output address process is coupled to a plurality of iteration variables generated by an iteration variable process, each iteration variable process having an associated with a bound and stride for each iteration variable, thereby generating an input address, a coefficient address, and an output address.