CNN Image Block Caching for Lower DRAM Bandwidth

The patent divides input images into multiple image blocks and processes them in a segmented manner. The CNN modeling process is split into multiple stages where different image blocks are processed using shared kernel weights, reducing the need to load entire large images into DRAM simultaneously. This segmentation allows accurate processing of large images while minimizing DRAM bandwidth requirements.

The patent performs preliminary actions by pre-loading and caching kernel weights and intermediate processing results into on-chip memory buffers before actual image processing begins. This preliminary preparation reduces the need for repeated DRAM accesses during the modeling process, thereby reducing overall DRAM bandwidth requirements while maintaining accuracy for larger input images.

The patent implements a universal kernel weight storage mechanism where the same kernel weights are reused across multiple image blocks and processing stages. This multi-functionality allows a single set of weights to serve multiple purposes, reducing the total memory capacity required and thereby lowering system cost while maintaining the ability to process large images for high accuracy.

The patent employs a nested memory hierarchy where on-chip buffers are nested within the processing unit, which is nested within the broader system architecture. This nested structure allows efficient use of limited on-chip memory resources to handle large image data, reducing the need for expensive high-bandwidth DRAM and associated system costs while maintaining CNN modeling accuracy.