CNN Convolution Architecture With Chained Partial Sums

The patent combines multiplication and addition operations into a single MAC operator that performs both operations sequentially. The operator first multiplies an input value by a filter coefficient, then adds a bias value in the same operational unit, eliminating the need for separate multiplication and addition operators. This merging reduces device footprint and complexity while maintaining full computational capability for convolutional layer operations.

The patent segments the convolutional layer computation into multiple stages, each handled by a dedicated MAC operator. Instead of using one large parallel processing unit with many addition operators, the computation is divided into sequential stages where each MAC operator processes a portion of the data. This segmentation allows parallel processing across multiple MAC operators while reducing the complexity and power consumption of each individual operator.

The patent implements preliminary alignment of input data with filter coefficients through the sequential operation structure of the MAC operator. Rather than requiring complex memory alignment mechanisms like line buffers, the data is prepared and aligned through the natural sequential flow of operations within each MAC operator. This approach achieves the necessary data alignment for parallel computation while avoiding the memory access complexity associated with line buffer architectures.