CNN Compiler for Programmable Functional Array Processors
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Solution Overview
Problem
Current hardware solutions for implementing convolutional neural networks (CNNs) face challenges due to inefficient memory usage and power consumption, as traditional load/store architectures are not optimized for CNNs, leading to the need for a specialized processor architecture that can efficiently process CNNs without relying on external memory.
Innovation Solution
A compiler is developed to convert CNNs into a memory-efficient format suitable for programmable functional array processors, utilizing intelligent memory buffers and core compute elements that optimize memory usage by storing only necessary data, eliminating redundant data movement, and allowing asynchronous operation of components, thereby reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional load/store architectures are used for CNN processing, then general-purpose computing is achieved, but memory efficiency deteriorates and power consumption increases
Solution Approach 1:
The processor is divided into multiple specialized functional units including convolution units, pooling units, normalization units, and activation units. Each unit is optimized for specific CNN operations, eliminating the need for general-purpose load/store instructions and reducing memory access overhead.
Solution Approach 2:
Intelligent memory buffers are introduced as intermediary components between external memory and compute units. These buffers store intermediate activation maps and weight data, reducing frequent accesses to external memory and thereby lowering power consumption while maintaining computational efficiency.
2Device complexity
If traditional memory architectures are used, then simplicity of design is maintained, but memory efficiency deteriorates due to redundant data movement
Solution Approach 1:
Data is pre-loaded into intelligent memory buffers before computation begins. Weight data and activation maps are staged in advance in the buffers, eliminating redundant data movement during the actual computation phase and reducing overall energy consumption.
Solution Approach 2:
The intelligent memory buffers maintain continuous data supply to compute units during processing. By keeping data in the buffers and enabling continuous computation without frequent memory access interruptions, the system eliminates redundant data movement while maintaining design simplicity.
3Area of stationary object
If external memory is used for CNN processing, then chip area is reduced, but processing speed deteriorates due to memory access latency
Solution Approach 1:
Intelligent memory buffers are nested within the processor chip, creating a hierarchical memory structure. The buffers are positioned between external memory and compute units, providing fast local storage for frequently accessed data and reducing access latency without significantly increasing chip area.
4Speed
If data is stored in primary memory for processing, then processing speed improves, but memory requirements increase power consumption
Solution Approach 1:
The intelligent memory buffers provide localized storage specifically for CNN data processing. By creating a dedicated storage region within the processor for activation maps and weight data, the system achieves fast access speeds while minimizing the energy required for memory storage and access.
Data Source
AI summary
Convolutional neural network compilers for programmable functional array processors are provided. One such compiler involves a method for fitting a convolutional neural network (CNN) to a CNN processor to be performed by a compiler, the method comprising: receiving a CNN; converting the CNN into a CNN graph; converting the CNN graph into a memory graph comprising graph primitives corresponding to a plurality of components of the CNN processor including a primary memory; performing a memory analysis to determine an amount of memory required in the primary memory for at least one of the graph primitives; identifying a plurality of tokens within the memory graph to form a token graph, each of the plurality of tokens comprising one or more of the graph primitives; and generating, using the plurality of identified tokens, configuration settings for each of the plurality of components of the CNN processor.