Convolutional Neural Network Layer Data Folding for Buffer Footprint Reduction
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Solution Overview
Problem
Convolutional neural networks face high operational demands, leading to inefficient hardware usage and resource wastage due to the need for padding and processing of feature data and convolution kernels, resulting in numerous invalid operations and resource inefficiencies.
Innovation Solution
The method involves padding and folding feature data and convolution kernels in specific dimensions to generate folded data and kernels, allowing for efficient convolution operations using fewer resources and improving channel utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If padding and processing of feature data and convolution kernels is performed in conventional manner, then convolution operation can be completed, but hardware resources are wasted due to numerous invalid operations
Solution Approach 1:
The patent extracts and removes the padding portions from the convolution operation process. By identifying that padding regions do not contribute to meaningful computation, the invention separates valid feature data processing from invalid padding processing, eliminating wasted hardware operations on padding regions while maintaining the necessary convolution functionality on valid data.
Solution Approach 2:
The patent segments the convolution operation into distinct valid and invalid portions. By dividing the feature data and convolution kernels into meaningful computational units that exclude padding regions, the invention enables targeted processing only of valid data segments, improving hardware resource utilization and reducing energy consumption from invalid operations.
2Productivity
If padding and processing of feature data and convolution kernels is performed in conventional manner, then convolution operation can be completed, but device complexity increases due to handling of padding operations
Solution Approach 1:
The patent extracts padding operations from the core convolution processing pipeline. By removing padding handling from the main computation flow and processing only valid feature data regions, the invention simplifies hardware design by eliminating the complexity of padding insertion, management, and processing while maintaining complete convolution functionality on valid data.
Solution Approach 2:
The patent segments the convolution processing into valid data paths that exclude padding operations. By dividing the computation into distinct valid region processing units, the invention reduces device complexity by eliminating hardware components needed for padding management while preserving the ability to complete full convolution operations on meaningful data.
3Productivity
If conventional convolution processing is performed, then operation completion is achieved, but buffer footprint is large due to storage of padded data
Solution Approach 1:
The patent extracts and removes padding data from buffer storage requirements. By identifying that padding regions do not contain meaningful information, the invention eliminates the need to allocate buffer space for storing and retrieving padding data, significantly reducing the buffer footprint while maintaining the ability to complete convolution operations on valid feature data.
Solution Approach 2:
The patent segments buffer storage into valid data regions only, excluding padding regions. By allocating buffer space solely for meaningful feature data and convolution kernel elements, the invention reduces the overall buffer footprint while ensuring sufficient capacity for completing full convolution operations on valid data through efficient memory management.
Data Source
AI summary
Disclosed are a method and an apparatus for performing an operation of a convolutional layer in a convolutional neural network. The method includes reading unfolded-feature-data and an original convolution kernel from DRAM, padding the unfolded-feature-data, folding the padded unfolded-feature-data in at least one dimension folded feature data, storing the folded feature data into a SRAM, folding the original convolution kernel in the at least one dimension to generate one or more folded convolution kernels, storing the one or more folded convolution kernels in the SRAM and reading the folded feature data and the one or more folded convolution kernels from the SRAM into a calculation circuit for performing a convolution operation on the folded feature data by using the one or more folded convolution kernels.