Configurable CNN Processor with Active Memory Buffer
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Solution Overview
Problem
Existing CNN processors face challenges such as reliance on external memory, inability to meet real-time requirements, and inefficiencies in power consumption and chip area usage.
Innovation Solution
A configurable processor architecture dedicated to implementing CNNs, featuring a plurality of core compute circuitry elements, an active memory buffer, and connections established according to a preselected dataflow graph, allowing for asynchronous operation and reduced memory needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GPU is used to process CNN inference, then computational throughput is improved, but power consumption increases significantly
Solution Approach 1:
The processor is divided into multiple core compute circuitry elements (e.g., 64 elements) that can be independently configured and operated. Each element can perform CNN computations, allowing the system to segment the computational workload across multiple specialized units rather than using a general-purpose GPU, thereby improving power efficiency while maintaining throughput.
Solution Approach 2:
The core compute circuitry elements are designed to be reconfigurable and can perform multiple CNN operations including convolutions, activations, and pooling functions. This multi-functionality allows a single specialized processor to handle various CNN workloads without requiring external memory or additional processing units, reducing overall power consumption compared to GPU solutions.
2Quantity of substance
If external memory is used for CNN processing, then data storage capacity is improved, but access time and power consumption increase
Solution Approach 1:
The processor integrates an active memory buffer directly within the processing unit, merging storage and computation functions into a single system. This eliminates the need for external memory access during CNN inference operations, as all required data can be stored and processed internally, thereby reducing memory access time and associated power consumption.
Solution Approach 2:
The active memory buffer is nested within the processor structure, with core compute circuitry elements positioned to access the buffer efficiently. This nested architecture allows data to be stored close to where it is processed, minimizing access latency and eliminating the need for external memory interfaces.
3Speed
If processor complexity is increased to meet real-time requirements, then processing speed is improved, but chip area usage increases
Solution Approach 1:
Each core compute circuitry element is designed with locally optimized resources including dedicated activation memory and configuration registers. This local quality allows each element to operate independently at high speed without requiring global communication across the chip, thereby achieving real-time processing speeds while minimizing the area required for interconnect structures.
Solution Approach 2:
The processor utilizes a dataflow-based architecture where computations are organized in parallel across multiple dimensions (spatial arrangement of core elements, temporal ordering of operations, and data flow paths). This dimensional organization allows the system to achieve high processing speeds through parallelism without requiring a proportional increase in chip area, as the parallel operations share common resources like the active memory buffer.
Data Source
AI summary
Configurable processors for implementing CNNs are provided. One such configurable CNN processor includes a plurality of core compute circuitry elements, each configured to perform a CNN function in accordance with a preselected dataflow graph, an active memory buffer, a plurality of connections between the active memory buffer and the plurality of core compute circuitry elements, each established in accordance with the preselected dataflow graph, a plurality of connections between the plurality of core compute circuitry elements, each established in accordance with the preselected dataflow graph, wherein the active memory buffer is configured to move data between the plurality of core compute circuitry elements via the active memory buffer in accordance with the preselected dataflow graph.