CNN Weight Conversion for Unified Bit-Width MAC Processing

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Solution Overview

Problem

Existing CNN architectures face inefficiencies in processing multiply-accumulate operations due to varying bit widths of weight coefficients, leading to increased circuit scale and power consumption, particularly in portable and embedded systems.

Innovation Solution

A technique that converts weight coefficients of varying bit widths to a standard bit width for processing using a common arithmetic unit, reducing the need for multiple types of arithmetic units and minimizing circuit scale.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple types of arithmetic units are used to process weight coefficients of different bit widths, then processing efficiency is improved, but device complexity and circuit scale increase

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidcircuit scale
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal arithmetic unit that can process weight coefficients of multiple bit widths (e.g., 4-bit and 8-bit) through a single unified structure. The arithmetic unit includes a multiplier and accumulator that can handle different data precisions by dynamically adjusting internal signal widths and saturation detection mechanisms, eliminating the need for separate arithmetic units for each bit width and thereby reducing circuit scale while maintaining processing efficiency

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the arithmetic unit by dynamically adjusting data widths and saturation thresholds based on the input weight coefficient bit width. When 4-bit weight coefficients are input, the system activates specific saturation detection circuits and adjusts accumulator width accordingly; when 8-bit weight coefficients are input, different parameter settings are applied. This parameter adaptation allows a single arithmetic unit to efficiently process different bit widths without requiring multiple dedicated units

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If multiple types of arithmetic units are used to process feature images and weight coefficients of different bit widths, then processing accuracy is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The universal arithmetic unit processes both 4-bit and 8-bit weight coefficients and feature images through a single unified structure, avoiding the need to power multiple specialized arithmetic units. The unit dynamically configures its internal parameters and saturation detection mechanisms based on the input data type, maintaining processing accuracy for different bit widths while reducing overall power consumption by keeping only one arithmetic unit active

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The arithmetic unit employs dynamic parameter adjustment where internal signal widths, saturation thresholds, and detection sensitivities are automatically modified based on the input data characteristics. This dynamic behavior allows the same hardware to accurately process different bit widths without requiring multiple static specialized units, thereby reducing power consumption while maintaining accuracy across varying processing requirements

Inventive Principle:
Principle #15Dynamics

3Loss of time

If weight coefficients are quantized to reduce bit width, then operation cost and processing time are reduced, but processing accuracy may be compromised

Engineering Contradiction:
Improveprocessing timeVSAvoidprocessing accuracy
Core Design Contradiction:
Loss of timeVSMeasurement precision

Solution Approach 1:

The patent introduces saturation detection circuits as intermediaries between the multiplier and accumulator. These detection circuits monitor the output of multiplication operations and prevent saturation errors by activating compensation mechanisms or adjusting processing parameters. This intermediary layer ensures that quantized 4-bit weight coefficients are processed accurately by detecting and correcting potential saturation issues, thereby maintaining processing accuracy while benefiting from the reduced bit width and faster computation

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260080673A1Information processing apparatus, information processing method, and non-transitory computer-readable storage medium
Publication Date: 2026.03.19 CANON KK
  • US20260080673A1 patent drawing
  • US20260080673A1 patent drawing
  • US20260080673A1 patent drawing

AI summary

An information processing apparatus comprises a conversion unit configured to, if a bit width of a weight coefficient in a first layer in weight coefficients in a plurality of layers is N bits, wherein N is a predetermined integer not less than 2, output the weight coefficient, and if the bit width of the weight coefficient is not N bits, output a weight coefficient of N bits obtained by converting the weight coefficient, and an operation unit configured to generate a feature image in a second layer based on a multiply-accumulate operation between the weight coefficient output by the conversion unit and a feature image in the first layer.