Bridge Fault Detection in CNOD Circuits
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Solution Overview
Problem
Boundary transistor defects in Continuous Oxide Diffusion (CNOD) semiconductor circuits are difficult to detect using existing Automatic Test Pattern Generation (ATPG) methods, leading to challenges in achieving high fault coverage.
Innovation Solution
The method involves extracting bridge pairs from neighboring cells in a CNOD circuit, modeling bridge faults as cell-level standalone leakage faults, and generating test patterns to detect defects, with the option to insert filler cells if fault detection coverage is not acceptable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If existing Automatic Test Pattern Generation (ATPG) methods are used, then testing can be automated, but boundary transistor defects in CNOD circuits cannot be effectively detected
Solution Approach 1:
The patent segments the circuit into individual cells with identifiable boundary transistors. By dividing the complex CNOD circuit into discrete cell units and focusing testing on boundary transistor behavior within each cell, the methodology enables automated detection of defects that were previously undetectable by conventional ATPG methods.
Solution Approach 2:
The patent introduces an intermediary modeling approach that represents boundary transistor defects as cell-level standalone leakage faults. This intermediary model acts as a bridge between the physical defect and the test pattern generation process, enabling automated testing to detect defects that directly affect the circuit's functional behavior.
2Reliability
If testing complexity is increased to detect boundary transistor defects, then fault detection coverage improves, but testing cost and time increase
Solution Approach 1:
The patent extracts and isolates boundary transistor behavior from the complex CNOD circuit by modeling defects as cell-level standalone leakage faults. This extraction simplifies the testing approach by focusing only on the critical boundary transistor elements rather than requiring comprehensive testing of the entire complex circuit, thereby improving fault detection coverage without proportionally increasing testing complexity.
3Productivity
If conventional ATPG test patterns are applied, then general fault detection is achieved, but boundary transistor defects remain undetected
Solution Approach 1:
The patent applies local quality by creating specialized test patterns targeted at boundary transistor defects in specific cell locations. Rather than using uniform test patterns across the entire circuit, the methodology generates location-specific test patterns that are optimized to detect boundary transistor defects, thereby improving measurement precision while maintaining productivity through automated generation.
Data Source
AI summary
Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.