CNT GAA Transistor Contacts Using Epitaxy for Lower Resistance

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Solution Overview

Problem

In the semiconductor industry, the development of three-dimensional designs such as gate all around (GAA) structures faces challenges in achieving low contact resistance and high performance due to the limitations of traditional materials, particularly in the integration of carbon nanotubes (CNTs) with source/drain contacts, leading to increased contact resistance and reduced device performance.

Innovation Solution

The integration of source/drain epitaxy structures between the CNTs and source/drain contacts, along with lightly-doped regions, to align the conduction bands and reduce contact resistance, combined with the use of carbon nanotubes with diameters in the range of 0.7 nm to 2.0 nm, facilitates band alignment and improves device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If carbon nanotubes are used as channel structures in semiconductor devices, then carrier mobility and electrostatic performance are improved, but contact resistance at the interface with source/drain contacts increases significantly

Engineering Contradiction:
Improvedevice performanceVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces source/drain epitaxy structures as intermediary layers between the carbon nanotube channel and the source/drain contacts. These epitaxy structures serve as a mediator that facilitates band alignment and reduces contact resistance, enabling efficient charge carrier transport while maintaining the high mobility benefits of CNT channels

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the electrical parameters at the CNT-contact interface by creating lightly-doped regions and epitaxial structures with specific doping concentrations. This changes the band structure and energy levels at the interface, enabling better band alignment and reducing Schottky barrier heights, thereby decreasing contact resistance

Inventive Principle:
Principle #35Parameter changes

2Productivity

If three-dimensional gate all around structures are implemented to increase device density, then manufacturing complexity and fabrication difficulty increase

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the gate structure into multiple functional components: a dummy gate structure formed initially, followed by separate formation of gate spacers on sidewalls, and subsequent replacement with metal gate materials. This segmentation allows each component to be optimized independently while maintaining the overall 3D GAA architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a preliminary dummy gate structure that is formed before the final metal gate structure. This dummy gate serves as a placeholder during critical fabrication steps such as epitaxy structure formation and contact creation, enabling subsequent replacement with the actual metal gate without compromising device performance or alignment

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces contact resistance at the CNTs, enhancing device performance by up to 30% compared to configurations without source/drain epitaxy structures, and allows for better band alignment, thereby improving the efficiency of charge carrier transport.

Implementation Method 1

Incorporating source/drain epitaxy structures and lightly-doped regions between CNTs and source/drain contacts, which are doped to achieve band alignment, reducing contact resistance

Methodology Applied
Scientific EffectBand alignment:

Data Source

PatentUS20230335617A1Semiconductor device and method for forming the same
Publication Date: 2023.10.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230335617A1 patent drawing
  • US20230335617A1 patent drawing
  • US20230335617A1 patent drawing

AI summary

A method includes forming a dielectric layer over a substrate; forming a carbon nanotube (CNT) over the dielectric layer; forming a dummy gate structure over the CNT; forming gate spacers on opposite sidewalls of the dummy gate structure; forming source/drain epitaxy structures on opposite sides of the dummy gate structure and in contact with opposite sidewalls of the CNT; replacing the dummy gate structure with a metal gate structure; and forming source/drain contacts over the source/drain epitaxy structures, respectively.