CNT GAA FET Source/Drain Contact With Dielectric-Embedded Doping

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Solution Overview

Problem

The semiconductor industry faces challenges in fabricating field-effect transistors (FETs) using carbon nanotubes (CNTs) due to difficulties in controlling the doping profile and integrating CNTs into a CMOS-compatible process flow.

Innovation Solution

The solution involves stacking aligned CNTs on a substrate to form a fin structure, using an embedded doping scheme with dielectric layers to induce charges in the CNTs, and employing a horizontal gate-all-around process flow compatible with CMOS technology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If carbon nanotubes are used to form fin structures, then carrier mobility and electrostatic performance are improved, but difficulty in controlling doping profile and integrating into CMOS process increases

Engineering Contradiction:
Improvecarrier mobilityVSAvoiddoping profile control
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

A dielectric layer is introduced as an intermediary between the carbon nanotube fin structure and the metal contact. This dielectric layer contains embedded dopant regions that serve as the doping mechanism, replacing traditional direct doping of the CNT channel. The dielectric mediator enables precise doping control through standard semiconductor fabrication techniques while maintaining the integrity of the CNT channel structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dopant regions are pre-formed within the dielectric layer before the metal contact is deposited. This preliminary doping action allows the doping profile to be established and controlled using standard photolithography and ion implantation techniques prior to final contact formation, enabling precise spatial and concentration control of the doping profile.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If carbon nanotubes are used to form fin structures, then electrostatic performance is improved, but device fabrication complexity increases

Engineering Contradiction:
Improveelectrostatic performanceVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dielectric layer serves multiple functions simultaneously: it provides electrical isolation between the metal contact and the CNT channel, contains the embedded dopant regions for carrier concentration control, and acts as a structural support for the fin configuration. This multi-functionality reduces the number of separate process steps needed compared to traditional approaches.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention changes the doping approach from direct CNT doping (which requires specialized low-temperature processes) to dielectric-embedded dopant regions that can be formed using standard high-temperature semiconductor fabrication parameters. This parameter change enables compatibility with existing CMOS manufacturing lines.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If embedded doping with dielectric layers is used, then carrier concentration is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecarrier concentrationVSAvoiddoping profile control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention replaces mechanical/direct physical doping of the CNT channel with an electromagnetic field-based approach where dopant atoms embedded in the dielectric layer generate electric fields that induce carrier concentration in the adjacent CNT channel. This substitution enables precise control through electrical field effects rather than direct material deposition on the CNT surface.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of gate-all-around FETs with improved carrier concentration and reduced contact resistance, facilitating their application in advanced technology nodes and logic circuits.

Implementation Method 1

an embedded doping scheme with dielectric layers to induce charges in the CNTs

Methodology Applied
Scientific EffectElectrostatic induction: Electrostatic Induction

Data Source

PatentUS20250151347A1Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor
Publication Date: 2025.05.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250151347A1 patent drawing
  • US20250151347A1 patent drawing
  • US20250151347A1 patent drawing

AI summary

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.