CNT Gate-All-Around Transistor Manufacturing via Trench Transfer
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Solution Overview
Problem
The fabrication of carbon nanotube (CNT)-based gate-all-around (GAA) field effect transistors (FETs) faces challenges such as low CNT density, inter-tube interactions that degrade performance, and the lack of a feasible high-density integration process into circuits.
Innovation Solution
A method for manufacturing GAA FETs using aligned CNTs with a gate dielectric layer and a gate electrode layer, where CNTs are stacked in trenches with anchor layers and formed using a sequential fabrication process that includes forming interfacial and gate dielectric layers, and applying a gate electrode layer, followed by transferring pre-fabricated CNT structures into trenches to avoid direct contact and subsequent performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CNTs are densely integrated to increase device density, then productivity and device density improve, but inter-tube interactions occur that degrade performance
Solution Approach 1:
The patent divides the CNT structure into individually isolated nanotubes within separate trenches, preventing inter-tube interactions while maintaining high density. Each CNT is independently enclosed by gate electrodes, creating segmented functional units that avoid harmful collective effects.
Solution Approach 2:
The patent introduces gate dielectric layers and gate electrodes as intermediary structures between CNTs. These intermediaries physically separate the CNTs electrically and structurally, allowing high-density integration without direct inter-tube interactions that would degrade performance.
2Manufacturing precision
If conventional fabrication processes are used, then ease of manufacture is maintained, but manufacturing precision and CNT alignment are insufficient
Solution Approach 1:
The patent performs preliminary actions by pre-forming gate dielectric layers, anchor structures, and trenches before introducing CNTs. This preliminary structuring creates precise alignment guides and containment features that automatically position CNTs with high precision during subsequent transfer steps.
Solution Approach 2:
The patent transitions from planar CNT placement to three-dimensional trench-based structures with gate electrodes wrapping around CNTs from multiple directions. This dimensional change enables precise spatial control and alignment that cannot be achieved with conventional two-dimensional fabrication processes.
3Quantity of substance
If CNTs are placed in direct contact to maximize density, then quantity of substance increases, but harmful inter-tube interactions degrade performance
Solution Approach 1:
The patent extracts CNTs from their original substrate and relocates them into isolated trench structures with gate electrodes. This extraction removes CNTs from environments where inter-tube interactions occur, placing them in controlled individual compartments that maintain density while eliminating harmful interactions.
Solution Approach 2:
The patent uses thin gate dielectric films and gate electrode structures to wrap around and isolate each CNT. These flexible thin-film structures provide electrical and physical separation between adjacent CNTs while maintaining compact high-density arrangements.
Data Source
AI summary
In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.