Self-Aligned Gate Carbon Nanotube Transistor Fabrication
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Solution Overview
Problem
Carbon nanotube field effect transistors (CNT FETs) face impractical gate geometries, which hinder their use in highly integrated digital applications due to non-uniform parasitic capacitance across the chip.
Innovation Solution
A self-aligned gate structure is achieved by forming source and drain contacts on a carbon nanotube substrate, creating a gap between them, and then removing a portion of the substrate to form a recess, allowing for anisotropic etching and deposition of a gate-all-around transistor with a high-k dielectric and conductive gate material surrounding the carbon nanotube bridge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate geometries are used in CNT FETs, then the device structure is simpler to manufacture, but the parasitic capacitance becomes non-uniform across the chip, hindering highly integrated digital applications
Solution Approach 1:
The substrate is removed in advance in the gap region between source and drain contacts before gate formation, creating a recess that pre-defines the gate-all-around geometry. This preliminary substrate removal enables subsequent uniform gate deposition and ensures consistent parasitic capacitance across all devices on the chip.
Solution Approach 2:
The gate structure transitions from a planar configuration to a three-dimensional gate-all-around geometry by removing substrate material and depositing gate material that surrounds the carbon nanotube channel from all sides. This dimensional change enables uniform electric field distribution and consistent parasitic capacitance.
2Reliability
If self-aligned gate structure is implemented, then uniform operation across the chip is achieved, but the manufacturing process becomes more complex with additional steps
Solution Approach 1:
Contacts are formed on the substrate before the substrate removal step, establishing the self-alignment reference for subsequent gate formation. This preliminary contact formation ensures that the gate will be automatically aligned with the contacts, achieving uniform transistor operation without requiring complex alignment procedures.
Solution Approach 2:
The previously formed contacts serve as self-alignment markers that automatically define the gate position and dimensions. The gate formation process uses the contacts as references, eliminating the need for separate alignment steps and ensuring uniform transistor characteristics across the chip.
3Power
If gate-all-around structure is formed with substrate removal, then low-voltage performance is improved, but the fabrication process requires additional etching and deposition steps
Solution Approach 1:
The substrate is removed in advance in the gap region to create a recess before gate material deposition. This preliminary substrate removal enables the gate material to conformally deposit around the carbon nanotube from all sides, forming the gate-all-around structure that improves low-voltage performance by enhancing gate control.
Solution Approach 2:
The fabrication process is segmented into distinct sequential steps: contact formation, substrate removal in the gap region, and gate material deposition. This segmentation allows each step to be optimized independently while maintaining the overall gate-all-around geometry required for low-voltage operation.
Data Source
AI summary
A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.