Carbon Nanotube Thin-Film Transistor With Reconfigurable Rectification
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Solution Overview
Problem
Two-dimensional semiconductor transistors exhibit weak rectification properties and are affected by asymmetric contacts introduced during manufacturing, limiting their reconfigurability and multifunctionality in integrated circuits.
Innovation Solution
A thin film transistor design incorporating a carbon nanotube structure with an interface charge layer between the carbon nanotube and gate insulating layer, which acts as a self-gating effect, modulating the Schottky barriers and enabling reconfigurable rectification characteristics through gate voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-dimensional semiconductor materials are used for transistor fabrication, then device reconfigurability and multifunctionality are improved, but rectification properties remain weak and are affected by asymmetric contacts
Solution Approach 1:
The patent introduces an asymmetric interface charge layer at the drain contact interface between the two-dimensional semiconductor and metal contact. This asymmetric charge distribution creates asymmetric Schottky barriers that enable strong rectification properties while preserving the reconfigurability of the device through gate control.
Solution Approach 2:
The patent modulates the rectification characteristics by changing the gate voltage parameter. The interface charge layer responds to gate voltage changes, dynamically adjusting the Schottky barrier heights and enabling reconfigurable rectification behavior without altering the physical structure.
2Ease of manufacture
If asymmetric contacts are introduced during manufacturing, then device fabrication is simplified, but rectification properties are degraded
Solution Approach 1:
The patent converts the harmful effect of asymmetric contacts (which normally degrade rectification) into a beneficial feature. By intentionally designing an asymmetric interface charge layer at the drain contact, the manufacturing asymmetry is transformed into a controlled mechanism for achieving strong rectification properties.
Solution Approach 2:
The patent applies local quality modification by creating a specific interface charge layer only at the drain contact interface. This localized modification affects only the rectification properties at the drain end while leaving the rest of the device structure and manufacturing process unchanged.
3Reliability
If interface charge layer is introduced to modulate Schottky barriers, then rectification factor increases to 10^3, but device structure becomes more complex
Solution Approach 1:
The patent introduces an interface charge layer as an intermediary between the two-dimensional semiconductor and the metal contact. This intermediary layer acts as a mediator that controls the Schottky barrier formation and enables high rectification without requiring complex multi-layer structures or additional processing steps.
Solution Approach 2:
The interface charge layer is formed through self-assembly or spontaneous charge redistribution at the contact interface during manufacturing. This self-service mechanism creates the desired asymmetric charge distribution without requiring additional deposition or patterning steps, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves significant reconfigurable rectification with a rectification factor of 103, allowing for bipolar channels and switching between forward and reverse rectification, while being sensitive to environmental charges and temperature-dependent interface charge redistribution.
Implementation Method 1
The interface charge layer between the carbon nanotube and gate insulating layer acts as a self-gating effect, modulating the Schottky barriers
Implementation Method 2
The carbon nanotube structure is disposed on a surface of the gate insulating layer away from the gate electrode. The source electrode and the drain electrode are arranged at intervals, and are electrically connected to the carbon nanotube structure, respectively
Data Source
AI summary
A thin film transistor includes a gate electrode, a gate insulating layer, a carbon nanotube structure, a source electrode and a drain electrode. The gate insulating layer is located on the gate electrode. The carbon nanotube structure is located on the gate insulating layer. The source electrode and the drain electrode are arranged at intervals and electrically connected to the carbon nanotube structure respectively. The thin film transistor further includes an interface charge layer, and the interface charge layer is located between the carbon nanotube structure and the gate insulating layer.