Co-integrating III-V and Ge Channels in Vertical FETs
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Solution Overview
Problem
The integration of III-V and Ge channels in vertical field effect transistors (VFETs) on a silicon substrate is challenging due to difficulties in forming high atomic percentage SiGe nanowires with minimal crystalline defects, which hinders the scaling of MOSFETs to smaller dimensions and increases middle-of-line fabrication complexity.
Innovation Solution
A method involving the formation of SiGe fins with a germanium content of 20-40% on a substrate, followed by condensation oxidation to increase the germanium content to 60-100%, allowing for the co-integration of III-V nanowires with increased germanium content, thereby enhancing electrostatic gate control and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high atomic percentage SiGe nanowires are formed to increase germanium content for better device performance, then electrostatic gate control and device density are improved, but crystalline defects increase and manufacturing precision deteriorates
Solution Approach 1:
The method performs preliminary actions by first forming SiGe fins with controlled low germanium content (20-40%) to establish a defect-minimized structural foundation, then subsequently increasing germanium content through condensation oxidation after the fin structure is already formed. This sequential approach allows the crystal lattice to be established before introducing higher germanium concentrations, preventing defect formation during the critical nucleation phase.
Solution Approach 2:
The invention dynamically changes the germanium concentration parameter through a two-stage process: first maintaining germanium content at 20-40% during fin formation to ensure crystal quality, then increasing it to 60-100% through condensation oxidation. This parameter transformation occurs after the critical crystal structure is established, allowing high germanium content to be achieved without compromising crystalline integrity.
2Ease of manufacture
If conventional fabrication methods are used to form MOSFETs, then manufacturing process is simple, but device density and performance are limited
Solution Approach 1:
The invention transitions from conventional planar (2D) MOSFET geometry to vertical (3D) VFET architecture by forming vertical channel fins that extend perpendicular to the substrate surface. This dimensional change enables increased device density and improved electrostatic control without requiring proportionally more complex fabrication processes, as the vertical structure can be integrated into existing CMOS fabrication flows.
3Reliability
If germanium content in SiGe fins is increased to improve device performance, then electrostatic gate control enhances, but formation of high quality nanowires becomes more difficult
Solution Approach 1:
The method performs preliminary actions by first forming SiGe fins with controlled low germanium content (20-40%) to establish a defect-minimized structural foundation, then subsequently increasing germanium content through condensation oxidation after the fin structure is already formed. This sequential approach allows the crystal lattice to be established before introducing higher germanium concentrations, preventing defect formation during the critical nucleation phase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the successful co-integration of III-V and Ge channels in VFETs, improving device density and performance by reducing crystalline defects and increasing the aspect ratio of the channel fin, thus alleviating fabrication complexity and enhancing electrostatic gate control.
Implementation Method 1
A condensation oxidation is performed to increase the first concentration level to a targeted first final concentration level and increase the second concentration level to a targeted second final concentration level.
Data Source
AI summary
Methods for forming cointegrated III-V and Ge channels for vertical field effect transistors are described. Aspects of the invention include forming a first fin and a second fin on a substrate, wherein the first fin includes a first material including a first semiconductor material at a first concentration level, and wherein the second fin includes a second material including a second semiconductor material at a second concentration. A condensation oxidation is performed to increase the first concentration level to a targeted first final concentration level and increase the second concentration level to a targeted second final concentration level. The second fin is replaced with a third fin including a third material including a combination of a group III element with a group V element.