Co-processor Checksum Module for Fault Attack Detection

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Solution Overview

Problem

Hardware accelerators used for computationally intensive tasks are vulnerable to fault attacks, even when both the main CPU and co-processor are secure, as attackers can modify computations, leading to uncertainty about the completion of tasks like AES functions.

Innovation Solution

An integrated circuit device with a main CPU core, a co-processor core, and a checksum generation module that processes data and returns a checksum value, allowing the main CPU to verify if the co-processor core has correctly performed AES functions by checking the validity of the checksum, and terminating execution if the checksum is invalid.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a hardware accelerator (co-processor core) is used to accelerate computation, then computation speed and efficiency are improved, but the system becomes vulnerable to fault attacks because results are passed between the hardware accelerator and main CPU

Engineering Contradiction:
Improvecomputation speedVSAvoidsecurity against fault attacks
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the co-processor core generates checksum values of its internal signals and returns them to the main CPU. The main CPU verifies these checksums to detect whether fault attacks have occurred during computation. This feedback loop enables the system to monitor and validate the integrity of accelerated computations without sacrificing performance.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces checksum values as an intermediary element between the co-processor core and main CPU. These checksums serve as a mediator that carries integrity information from the co-processor back to the main CPU, allowing verification of computation integrity without directly exposing sensitive internal states or slowing down the primary computation flow.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If checksum verification is implemented to detect fault attacks, then security and reliability are improved, but the system complexity increases due to additional verification mechanisms

Engineering Contradiction:
Improvefault attack detectionVSAvoidsystem structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The checksum generation module within the co-processor core serves multiple functions: it computes checksums of internal signals for fault detection, and these same checksums also serve as verification data that can identify whether specific operations (like AES functions) were actually executed. This multi-functionality reduces the need for separate verification mechanisms and minimizes system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The co-processor core performs self-verification by automatically generating checksums of its own internal signals and returning them to the main CPU. This self-service approach eliminates the need for external monitoring hardware or complex verification protocols, as the co-processor independently provides its own integrity validation.

Inventive Principle:
Principle #25Self-service

3Reliability

If the co-processor core returns checksum values for verification, then fault attack detection capability is improved, but the communication overhead between main CPU and co-processor increases

Engineering Contradiction:
Improveintegrity verificationVSAvoidcommunication overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The checksum generation module computes checksums of internal signals during the normal operation of the co-processor core, before the computation results are returned to the main CPU. This preliminary computation of checksums allows the verification process to occur in parallel with the main computation flow, minimizing additional communication overhead and time loss.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9929858B2Method and system for detecting fault attacks
Publication Date: 2018.03.27 NXP BV
  • US9929858B2 patent drawing
  • US9929858B2 patent drawing
  • US9929858B2 patent drawing

AI summary

In an embodiment, an integrated circuit (IC) device for detecting fault attacks is disclosed. In the embodiment, the IC device includes a main CPU core, memory coupled to the main CPU core, and a co-processor core including a checksum generation module, the co-processor core coupled to the main CPU core, wherein the main CPU core is configured to direct the co-processor core to process data from the memory and the co-processor core is configured to process the data, in part, by feeding internal signals to the checksum generation module and wherein the co-processor core is further configured to return a checksum value generated by the checksum generation module to the main CPU core.