Co-processor for complex arithmetic processing with parallel memory access
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Solution Overview
Problem
Current radio communication systems face challenges in being flexible and efficient for multiple radio communication methods due to high space overhead and low flexibility in dedicated hardware circuits, and high power consumption and processing time in software processing approaches.
Innovation Solution
A co-processor for complex arithmetic processing that includes a complex arithmetic circuit and a memory controller with trace and preprocessing circuits, enabling parallel execution of complex arithmetic operations and normalization, and autonomously generating addresses to hide memory access latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated hardware circuits are implemented for each radio communication method, then high-speed performance and low power consumption are achieved, but space overhead increases and flexibility decreases
Solution Approach 1:
The patent implements a universal co-processor architecture that can execute multiple radio communication methods (CDMA, OFDM, etc.) through a single hardware circuit. The co-processor uses configurable parameters and a unified processing engine that adapts to different communication standards, eliminating the need for separate dedicated circuits for each method while maintaining high-speed performance.
Solution Approach 2:
The co-processor employs dynamic configuration capabilities where processing parameters, arithmetic operation types, and data units can be changed at runtime. This dynamic adaptability allows the same hardware circuit to efficiently process different radio communication methods by reconfiguring its operational characteristics rather than requiring static dedicated circuits for each method.
2Productivity
If dedicated hardware circuits are implemented for each radio communication method, then high-speed performance is achieved, but circuit space overhead increases
Solution Approach 1:
The patent implements a universal co-processor architecture that can execute multiple radio communication methods (CDMA, OFDM, etc.) through a single hardware circuit. The co-processor uses configurable parameters and a unified processing engine that adapts to different communication standards, eliminating the need for separate dedicated circuits for each method while maintaining high-speed performance.
Solution Approach 2:
The patent merges multiple functionally similar but method-specific processing circuits into a single co-processor unit. By combining the processing engines for different radio communication methods into one unified hardware circuit with configurable parameters, the patent reduces the total circuit space required while maintaining the processing capabilities of individual dedicated circuits.
3Adaptability or versatility
If software processing is used instead of dedicated hardware circuits, then flexibility increases, but power consumption and processing time increase
Solution Approach 1:
The patent introduces a co-processor as an intermediary hardware unit between the main processor and memory. This co-processor handles complex arithmetic operations in hardware, providing speed comparable to dedicated circuits while maintaining the flexibility of software-controlled processing. The co-processor executes instructions from the main processor, bridging the gap between software flexibility and hardware performance.
4Measurement precision
If normalization processing is performed sequentially after complex arithmetic operations, then processing accuracy is maintained, but processing time increases
Solution Approach 1:
The patent implements a trace circuit that performs preliminary monitoring of arithmetic result data during the complex arithmetic operations. The trace circuit detects normalization coefficients in real-time as data flows through the processing pipeline, enabling normalization to be performed concurrently rather than sequentially. This preliminary detection allows the normalization coefficient to be ready when needed, maintaining accuracy while reducing processing time.
Solution Approach 2:
The patent ensures continuous processing by implementing a pipeline architecture where complex arithmetic operations and normalization monitoring occur simultaneously. The trace circuit continuously monitors arithmetic results as they are generated, and the memory controller continuously prepares normalized data for output, eliminating idle periods and maintaining uninterrupted processing flow throughout the modulation/demodulation pipeline.
Data Source
AI summary
In order to enable to quickly and efficiently execute, by one system, various modulation/demodulation/synchronous processes in a plurality of radio communication methods, a co-processor (22) for complex arithmetic processing, which forms a processor system (100), includes a complex arithmetic circuit (22) that executes for complex data a complex arithmetic operation required for radio communication in accordance with an instruction from a primary processor (10), and a memory controller (20, 21) that operates in parallel with the complex arithmetic circuit and accesses a memory. A trace circuit provided in the complex arithmetic circuit (22) monitors arithmetic result data for first complex data series sequentially read from the memory, and detects a normalization coefficient for normalizing the arithmetic result data.