Co-Resident Network Switching with Event-Driven Packet Processing

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Solution Overview

Problem

Current network switching technologies face inefficiencies due to interrupt-driven kernel packet management, which degrades network performance in terms of throughput and latency, especially in virtualized systems where packet routing and management are dependent on specific kernel implementations.

Innovation Solution

A network switching apparatus with a layer 2 switch coupled to co-resident data-plane and network interface controllers, where packet management is implemented using a combination of hardware and software entities, allowing for efficient packet processing and switching between NICs, PKIs, and PKOs on a single chip, minimizing overhead and optimizing chip resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If interrupt-driven kernel packet management is used, then packet processing can be performed, but network performance (throughput and latency) deteriorates

Engineering Contradiction:

Improvepacket processing capabilityVSAvoidnetwork throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments packet processing into two distinct paths: interrupt-driven path for control packets and event-driven path for data packets. This segmentation allows the system to handle different packet types efficiently, improving overall network throughput while maintaining reliable packet processing capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an event-driven intermediary layer between the NIC and the kernel. This intermediary processes data packets through event handlers rather than direct interrupts, reducing kernel overhead and improving network throughput while maintaining packet processing reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If interrupt-driven kernel packet management is used, then packet processing can be performed, but latency increases

Engineering Contradiction:

Improvepacket processing capabilityVSAvoidpacket latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments packet processing into interrupt-driven path for control packets and event-driven path for data packets. This segmentation reduces latency for data packets by handling them through the event-driven path, which avoids the overhead of interrupt context switches and kernel mode transitions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-allocating packet buffers and setting up event handlers before packets arrive. This preparation eliminates the need for buffer allocation and handler setup during packet processing, significantly reducing packet latency while maintaining processing capability.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If packet management is implemented in kernel software, then general-purpose processing is achieved, but performance is low

Engineering Contradiction:

Improvekernel software compatibilityVSAvoidpacket processing performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces the mechanical kernel software processing mechanism with a hardware-based event-driven mechanism. The NIC and event handlers process packets in hardware or near-hardware, eliminating the performance limitations of kernel software while maintaining adaptability through programmable event handlers.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Device complexity

If traditional NIC architecture is used, then simple network interface functionality is provided, but network performance is degraded

Engineering Contradiction:

ImproveNIC architecture simplicityVSAvoidnetwork throughput

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent merges the NIC with integrated switch fabric and event handling capabilities into a single co-resident architecture. This merging provides enhanced network performance through hardware-based packet switching and event-driven processing while maintaining relative architectural simplicity through integration rather than multiple separate components.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9866657B2Network switching with layer 2 switch coupled co-resident data-plane and network interface controllers

Publication Date: 2018.01.09 MARVELL ASIA PTE LTD

AI summary

A system network switching with layer 2 switch communicatively coupled co-resident data-plane and network interface controllers embodying a method for, receiving a packet from a communication network at the layer 2 switch; parsing the packet; and determining in accordance with a content of the parsed packet whether the packet is to be switched to one of one or more medium access controllers, or one of one or more packet input processors, or one of one or more network interface controllers of a network interface resource comprising the one or more packet input processors, one or more packet output processors, the one or more network interface controllers, and the layer 2 switch, implemented on a chip are disclosed.