Co-Ru Lined Metal Interconnect Structure for Lower RC Delay
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Solution Overview
Problem
As device dimensions shrink, increased line resistance and parasitic capacitance lead to slower chip speeds and higher power consumption, and while low-k dielectric materials help, the use of air gaps in integrated circuits is hindered by structural weakness and mechanical instability.
Innovation Solution
A method for fabricating metal interconnect structures using a Co-Ru alloy liner between a titanium nitride barrier layer and a copper metal layer, with optional additional liners, to form a robust and low-capacitance interconnect system, which includes forming a dielectric layer, trenches, and planarizing the metal and liner layers to create a stable metal interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If air gap structures are used to reduce dielectric constant, then RC signal delay is reduced, but mechanical strength is reduced and structural deformation occurs
Solution Approach 1:
The patent introduces a low-k dielectric material as an intermediary substance between metal interconnect lines, replacing air gaps. This low-k material has a dielectric constant between 1.0 (air) and 4.0 (silicon dioxide), providing reduced capacitance while maintaining mechanical structural integrity. The low-k dielectric acts as a mediator that achieves the electrical performance of air gaps without their mechanical weaknesses.
2Productivity
If device dimensions are reduced to increase packing density, then more conductive lines can be packed, but line resistance increases and RC delay worsens
Solution Approach 1:
The patent changes the dielectric parameter (dielectric constant k-value) of the material between interconnect lines. By using low-k dielectric materials with k-values significantly lower than conventional silicon dioxide, the patent reduces parasitic capacitance C in the RC delay equation. This allows continued scaling of device dimensions and increased packing density without proportionally increasing RC signal delay.
3Stability of the object's composition
If conventional silicon dioxide dielectric is used, then thermal and chemical stability is maintained, but dielectric constant is too high for further RC reduction
Solution Approach 1:
The patent changes the dielectric constant parameter by transitioning from conventional silicon dioxide (k≈4.0-4.5) to low-k dielectric materials with k-values ranging from 2.0 to 3.0 or lower. This parameter change reduces the capacitance component of RC delay while the patent addresses stability concerns through proper material selection and integration processes that maintain thermal and chemical compatibility with existing semiconductor manufacturing.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.