Hardware Co-Simulation Breakpoint Control for Electronic Design Validation
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Solution Overview
Problem
In high-level modeling systems, synchronizing software and hardware co-simulation platforms for electronic designs is complicated by timing issues and limited visibility into signal states, requiring additional circuitry and polling mechanisms.
Innovation Solution
Incorporating breakpoint blocks with user-defined conditions in the design, allowing for controlled advancement of the clock signal on a hardware-based co-simulation platform, with user-selectable modes to manage clock progression after a breakpoint condition is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polling mechanisms and additional circuitry are added to synchronize HLMS with hardware co-simulation platform, then synchronization capability is improved, but device complexity increases
Solution Approach 1:
The hardware co-simulation platform autonomously generates trace data and manages its own state information without requiring external polling mechanisms. The platform self-services by internally tracking signal states and making this information available through predefined interfaces, eliminating the need for additional synchronization circuitry and polling infrastructure.
Solution Approach 2:
A trace data buffer acts as an intermediary between the hardware co-simulation platform and the HLMS. This buffer captures and stores trace data from the hardware platform, making it accessible to the HLMS without requiring direct synchronization mechanisms. The intermediary handles data translation and timing coordination, reducing complexity in the main system.
2Measurement precision
If trace data buffering is implemented to provide visibility into hardware signal states, then measurement capability is improved, but device complexity increases
Solution Approach 1:
The trace data buffering capability is merged with the existing hardware co-simulation platform infrastructure. The trace buffer utilizes available hardware resources such as existing memory blocks and logic elements within the platform, combining multiple functions (simulation, tracing, and data storage) into a unified system rather than adding separate dedicated components.
Solution Approach 2:
The trace data buffer is designed with multi-functionality, serving both as a data storage mechanism and as a measurement interface. The same buffering infrastructure supports various measurement and observation needs across different signal states and simulation conditions, reducing the need for specialized circuitry for each measurement requirement.
Data Source
AI summary
Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of the design, and the design further includes at least one simulation block and at least one co-simulation block. The simulation block is simulated on a software-based simulation platform, and the co-simulation block and the breakpoint block are co-simulated on a hardware-based co-simulation platform. Advancement of a clock signal to the co-simulation block on the hardware-based co-simulation platform is inhibited in response to satisfaction of the breakpoint condition. After inhibiting the clock signal, advancement of steps of the clock signal is controlled on the co-simulation platform in one of a plurality of user-selectable clock advancement modes.