Co-support Module for Compact Microelectronic Assembly

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional microelectronic packages occupy excessive space due to large terminal areas, hindering compact arrangements necessary for advanced portable devices and data servers, and are limited in functional flexibility for interconnecting different types of microelectronic elements.

Innovation Solution

A modular circuit panel system with co-support contacts configured to connect with various microelectronic assemblies, allowing for flexible arrangement of command and address information transfer across different types of microelectronic elements, including DDRx and LPDDRx, through adjustable sampling rates and contact assignments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional microelectronic packages use large terminal areas for connections, then reliable electrical connections are achieved, but the package occupies excessive space on the circuit panel

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidpackage area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar terminal arrangements to three-dimensional vertical interconnections using through-substrate vias and stacked chip architectures. This allows electrical connections to extend in the vertical dimension rather than requiring large horizontal terminal areas, thereby reducing the package footprint while maintaining connection reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested packaging where multiple chips are stacked vertically within a single package footprint. Smaller chips are positioned at different height levels and interconnected through vertical vias, allowing multiple functional elements to occupy the same planar area while maintaining reliable electrical connections through the stacked configuration

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If conventional packages are designed for specific microelectronic element types, then optimized performance is achieved, but functional flexibility for interconnecting different types of elements is limited

Engineering Contradiction:
Improveperformance optimizationVSAvoidfunctional flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent designs a universal package substrate with standardized through-substrate via patterns and interconnection architectures that can accommodate multiple types of microelectronic chips. The same package structure and connection methodology can be used with different chip types (e.g., logic chips, memory chips, sensors), providing functional flexibility while maintaining optimized performance through consistent electrical interconnection standards

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8848392B2Co-support module and microelectronic assembly
Publication Date: 2014.09.30 ADEIA SEMICON TECH LLC
  • US8848392B2 patent drawing
  • US8848392B2 patent drawing
  • US8848392B2 patent drawing

AI summary

A module is configured for connection with a microelectronic assembly having terminals and a microelectronic element. The module includes a circuit panel bearing conductors configured to carry command and address information, co-support contacts coupled to the conductors, and module contacts coupled to the conductors. The co-support contacts include first contacts having address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the first contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts at a second sampling rate greater than the first sampling rate.