Co-support XFD Packaging with Aperture Terminals

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Solution Overview

Problem

Conventional microelectronic packages occupy excessive space due to lengthy electrical connections between chips and circuit panels, leading to signal degradation and performance issues in high-frequency operations.

Innovation Solution

The design incorporates a dielectric element with apertures and terminals that allow for reduced stub lengths by aligning first and second microelectronic elements with modulo-X symmetry, enabling shorter electrical connections and improved signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional packages use columns of terminals at peripheral edges with wire bonds extending through central region, then electrical connections can be established between chips and circuit panel, but the package occupies excessive area on the circuit panel

Engineering Contradiction:
Improvepackage area on circuit panelVSAvoidelectrical connection length
Core Design Contradiction:
Area of stationary objectVSLength of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional peripheral terminal arrangement to a three-dimensional structure by placing terminals on both the top and bottom surfaces of the package substrate. This allows electrical connections to be established in multiple spatial dimensions, reducing the footprint area on the circuit panel while maintaining connection functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The terminal columns are segmented and distributed across different surfaces (top and bottom) of the package substrate rather than concentrated at peripheral edges. This segmentation allows for more efficient space utilization and shorter connection paths to the circuit panel.

Inventive Principle:
Principle #1Segmentation

2Reliability

If wire bonds extend through central region to connect contacts to peripheral terminal columns, then electrical connections are established, but signal degradation occurs in high-frequency operations

Engineering Contradiction:
Improvesignal integrityVSAvoidelectrical connection length
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent extracts the terminal columns from the peripheral edge locations and repositions them on the top and bottom surfaces of the package substrate. This extraction eliminates the need for long wire bonds extending through the central region, thereby reducing connection length and improving signal integrity for high-frequency operations.

Inventive Principle:
Principle #2Taking out (Extraction)

3Area of stationary object

If terminals are placed in peripheral columns only, then conventional packaging structure is maintained, but the package area on circuit panel is excessive

Engineering Contradiction:
Improvepackage area on circuit panelVSAvoidpackage structure complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent utilizes the third dimension by placing terminals on both top and bottom surfaces of the package substrate. This dimensional change reduces the required package area on the circuit panel while the overall structural complexity remains manageable through systematic terminal distribution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9293444B2Co-support for XFD packaging
Publication Date: 2016.03.22 ADEIA SEMICON TECH LLC
  • US9293444B2 patent drawing
  • US9293444B2 patent drawing
  • US9293444B2 patent drawing

AI summary

A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements.