Co-verification Interface for Mixed Physical Virtual System Verification
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Solution Overview
Problem
Current design verification systems for system-on-chip (SoC) modules are inadequate due to slow performance, high costs, and difficulties in accurately modeling hardware components, particularly in cycle-level accuracy and debugging, which hinders efficient co-verification of hardware and software components.
Innovation Solution
A design verification system that couples physical and virtual elements via a flexible communication system, utilizing co-verification interfaces and a layered protocol stack to facilitate communication and debugging, allowing for faster verification and easier transition from virtual to physical forms, thereby improving verification speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If event-driven gate-level logic simulators are used to model hardware components, then hardware verification can be performed, but performance is too slow (1-1000 cycles per second) to operate software components effectively
Solution Approach 1:
The patent creates a virtual environment that copies physical hardware behavior through software models. Virtual elements replicate the functional behavior of physical hardware components, allowing software components to be executed and verified without requiring actual physical hardware or slow gate-level simulators. This virtual copying enables fast execution while maintaining verification accuracy.
Solution Approach 2:
The patent replaces the mechanical simulation process (event-driven gate-level logic simulators) with a software-based virtual execution environment. Instead of using slow hardware simulators to model hardware behavior, the system uses software models that can execute at native processor speeds, substituting the mechanical simulation mechanism with a more efficient software execution approach.
2Productivity
If instruction set simulators are used to model hardware components at instruction level, then software components can operate at higher speeds (10,000-100,000 cycles per second), but cycle level accuracy is lost which is necessary for media processing systems and real-time embedded systems
Solution Approach 1:
The patent implements a dynamic virtual execution environment that adapts its level of detail based on the verification requirements. The virtual elements can operate at different levels of abstraction and precision, allowing the system to achieve both high-speed execution and cycle-level accuracy when needed. The environment dynamically adjusts the modeling fidelity to match the specific verification task requirements.
Solution Approach 2:
The patent changes the operational parameters of the verification system by introducing virtual elements that can execute at native processor speeds rather than being constrained by simulator clock rates. This parameter change enables the system to achieve both high productivity and high measurement precision simultaneously, as the virtual elements can replicate physical hardware behavior accurately while executing at full speed.
3Productivity
If custom prototypes are produced using field programmable gate arrays, then hardware components can be verified at full speed, but the system is limited to small modular hardware components and requires expensive custom processors
Solution Approach 1:
The patent uses virtual elements as software copies of physical hardware components, eliminating the need for expensive FPGAs and custom processors. These virtual models can be instantiated on standard computing platforms, providing full-speed verification capability without requiring specialized hardware infrastructure or complex system configurations.
Solution Approach 2:
The patent replaces expensive, complex FPGAs and custom processors with inexpensive, general-purpose computing platforms. The virtual elements can be deployed on standard off-the-shelf hardware, significantly reducing the cost and complexity of the verification system while maintaining full-speed verification capability.
4Ease of operation
If physical platform development prototype boards are used, then hardware components can be independently debugged, but specially-developed testbench programs are required and components are difficult to debug and revise once synthesized
Solution Approach 1:
The patent creates virtual copies of hardware components that can be independently debugged using standard software debugging tools. These virtual elements can be modified and revised without requiring physical hardware changes or specially-developed testbench programs, enabling faster iteration and reducing development time compared to physical prototype boards.
Data Source
AI summary
A design verification system for developing electronic systems and methods for manufacturing and using same. The design verification system comprises a plurality of system elements, including at least one physical (or hardware) element and/or at least one virtual (or software) element, which are coupled, and configured to communicate, via a general communication system. Since the system elements may be provided on dissimilar development platforms, each system element is coupled with the communication system via a co-verification interface, which is provided as a layered protocol stack to assure portability and flexibility. Through use of the co-verification interface, the design verification system can be configured to support a wide variety of mixed physical/virtual systems.