COAG Gate Insulating Cap Layout for Lower Fringe Capacitance
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of multi-gate transistors to the 10 nanometer node or sub-10 nanometer range, leading to yield issues and unoptimized fringe capacitance, particularly in the formation of gate contacts over active gate regions.
Innovation Solution
The implementation of contact over active gate (COAG) structures with widened and lower capacitance gate insulating cap layers, utilizing a low-k liner and thinner nitride etch stop layer to reduce fringe capacitance and eliminate yield issues, allowing direct contact formation over active transistor gates without the need for additional gate contact layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistors, then existing infrastructure compatibility is maintained, but manufacturing precision and yield are limited at 10 nanometer node or sub-10 nanometer range
Solution Approach 1:
The patent modifies the gate insulating cap layer parameters by reducing its thickness and lowering its dielectric constant (using low-k materials). This changes the electrical and physical parameters of the structure to reduce fringe capacitance and enable precise contact formation at 10nm node, thereby improving manufacturing precision and yield without requiring complete process overhaul
Solution Approach 2:
The patent applies different materials and thicknesses to different regions of the gate structure. Specifically, a thinner gate insulating cap layer is used over the active gate region where contact is needed, while maintaining appropriate insulation elsewhere. This localized modification enables precise contact formation while maintaining overall device performance
2Reliability
If conventional gate insulating cap layers are used, then gate insulation is maintained, but fringe capacitance is increased and layout area is wasted
Solution Approach 1:
The patent reduces the thickness of the gate insulating cap layer and uses low-k dielectric materials with lower capacitance values. This directly reduces the fringe capacitance between the gate and surrounding structures, eliminating the harmful capacitive coupling while maintaining sufficient insulation through optimized thickness and material selection
Solution Approach 2:
The gate insulating cap layer is made thinner specifically over the active gate region where contact is formed, while maintaining adequate thickness in other regions. This localized thinning reduces fringe capacitance in the critical area without compromising overall gate insulation integrity
3Ease of manufacture
If additional gate contact layers are used, then contact formation is simplified, but device complexity and layout area increase
Solution Approach 1:
The patent removes the separate gate contact layer from the structure. Instead, the gate contact is formed directly through the gate electrode using the thinned gate insulating cap layer as the contact opening layer. This eliminates the additional processing step of forming a separate gate contact layer, reducing device complexity while maintaining ease of manufacture through self-aligned contact formation
Solution Approach 2:
The gate insulating cap layer serves multiple functions: it provides gate insulation, acts as the contact opening layer, and enables self-aligned contact formation. By making the gate insulating cap layer thinner and using low-k materials, it becomes multi-functional, eliminating the need for separate gate contact layers and reducing overall device complexity
Data Source
AI summary
Contact over active gate (COAG) structures with widened and lower capacitance gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using widened and lower capacitance gate insulating cap layers, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. An epitaxial source or drain structure is coupled to the vertical stack of horizontal nanowires or the fin. A gate stack is over the vertical stack of horizontal nanowires or the fin, the gate stack including a gate dielectric and a gate electrode. A gate dielectric spacer is along sides of the gate stack. A gate insulating cap structure is on the gate stack and extending laterally beyond the gate stack, the gate insulating cap structure vertically over the gate dielectric spacer, and the gate insulating cap structure including a dielectric liner and a dielectric fill.