COAG Gate Insulating Cap Layers for Uniform Self-Aligned Contacts
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Solution Overview
Problem
The scaling of multi-gate transistors to smaller dimensions for advanced integrated circuit fabrication faces challenges due to variability in conventional fabrication processes, limiting the ability to extend into the 10 nanometer node or sub-10 nanometer range, and requires new methodologies or integration of new technologies to optimize performance.
Innovation Solution
The implementation of contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, which allows for self-aligned gate contact formation over active gate regions, simplifying the processing scheme and reducing variability by eliminating the need for recessing and polish operations, and enabling trench contact formation with distinct dielectric cap layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing manufacturing methods can be maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node and below
Solution Approach 1:
The gate insulating cap layer is deposited conformally over the gate structure before any contact formation or recess operations. This preliminary deposition ensures that the cap layer is already in place and uniformly distributed, preventing variability issues that would arise from attempting to form contacts first and then adding the cap layer.
Solution Approach 2:
The patent extracts and eliminates the need for separate gate recess processes and polish operations that were previously required. By using conformal deposition followed by selective etching of the gate spacers, the complex multi-step process of recessing and polishing is removed, simplifying manufacturing and improving precision.
2Area of stationary object
If gate contacts are formed over active gate portions, then layout area is optimized, but manufacturing complexity increases due to variability in gate insulating cap layers
Solution Approach 1:
The patent changes the deposition parameters and process conditions to achieve conformal coverage of the gate insulating cap layer. By controlling deposition parameters such as temperature, pressure, and material flow rates, uniform cap layers are formed even over complex three-dimensional gate structures, eliminating variability without increasing process complexity.
Solution Approach 2:
The conformal deposition process automatically adapts to the underlying gate structure geometry, with the cap layer self-adjusting to conform to sidewalls and surfaces. This self-service characteristic eliminates the need for separate alignment and adjustment steps, maintaining simplicity while enabling optimized layout area utilization.
3Quantity of substance
If multi-gate transistors are scaled down, then device density increases, but fabrication process constraints become overwhelming
Solution Approach 1:
The fabrication process is segmented into distinct functional steps: conformal deposition of the gate insulating cap layer, selective etching of gate spacers, and formation of contact openings. This segmentation allows each step to be optimized independently, making the overall process more manageable even as device density increases through multi-gate transistor scaling.
Solution Approach 2:
The patent transitions from planar processing to three-dimensional conformal deposition, where the gate insulating cap layer wraps around the gate structure vertically. This dimensional change allows better control over cap layer thickness and uniformity, enabling scaled-down multi-gate transistors without proportionally increasing fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a simpler, cleaner, and more uniform process for forming gate contact structures, reducing layout waste and allowing direct contact formation on active transistor gates without shorting to adjacent regions, thereby enhancing circuit density and performance.
Implementation Method 1
deposition of a conformal gate insulating cap layer
Implementation Method 2
deposition of a conformal gate insulating cap layer
Implementation Method 3
recessing gate spacers
Implementation Method 4
uniform and conformal gate insulating cap layers
Data Source
AI summary
Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.