COAG Etch Stop Structure for Self-Aligned Gate Contacts
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Solution Overview
Problem
The challenge of fabricating integrated circuits at the 10 nanometer node and smaller nodes is hindered by variability in conventional fabrication processes, leading to constraints on semiconductor processes and the need for new methodologies to form reliable contacts to gate electrodes without wasting layout space or increasing gate dimensions.
Innovation Solution
The implementation of contact over active gate (COAG) structures with etch stop layers, allowing for the formation of gate contact vias directly on active transistor gates, eliminating the need for separate gate contact layers and reducing layout space by using etch stop layers for selective via contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node and smaller
Solution Approach 1:
The fabrication process is divided into distinct segments: forming the gate structure with insulating cap layer, creating etch stop layers with specific materials, and performing selective etching operations. Each segment addresses specific precision requirements independently, allowing tight control at each stage rather than relying on a monolithic conventional process.
Solution Approach 2:
The patent introduces specific material parameters (etch stop layers with selective etch rates, insulating cap layer materials) and process parameters (selective etching conditions, via dimensions) to achieve the required precision. These parameter changes enable differentiation between gate regions and contact regions, achieving sub-10 nanometer precision.
2Area of moving object
If separate gate contact layers are used, then ease of manufacture is maintained, but area of moving object increases due to wasted layout space
Solution Approach 1:
The gate contact structure is merged with the gate electrode structure by forming the contact through the insulating cap layer directly to the gate electrode, eliminating the need for separate gate contact layers. This integration reduces layout area while the self-aligned nature of the process maintains fabrication simplicity.
Solution Approach 2:
The insulating cap layer serves multiple functions: it provides electrical isolation, defines the gate contact region, and enables self-aligned contact formation. This multi-functionality eliminates the need for dedicated gate contact layers while maintaining ease of manufacture through a unified process approach.
3Length of moving object
If gate dimensions are increased to accommodate contacts, then ease of operation is maintained, but length of moving object increases
Solution Approach 1:
The self-aligned contact formation process uses the gate structure itself and the insulating cap layer to automatically define the contact position and dimensions. The etch stop layers and selective etching processes ensure that contacts are formed precisely where needed without requiring increased gate dimensions or additional alignment steps, maintaining both compact size and operational reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances yield and reduces standard cell area by enabling self-aligned gate contact formation, improving the reliability and efficiency of integrated circuit fabrication at advanced technology nodes.
Implementation Method 1
an etch stop layer is formed over the gate insulating cap layer and the trench contact insulating cap layer. The etch stop layer may be the same material as the trench contact insulating cap layer. A contact hole is formed through the interlayer dielectric layer and the etch stop layer to expose a top surface of the gate insulating cap layer
Data Source
AI summary
Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.