Coalesced Page Table Entries for Memory Translation
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Solution Overview
Problem
Current memory management systems face inefficiencies in tracking changing physical addresses when pages are moved between secondary and primary memory, leading to increased latency and communication traffic due to the need for frequent updates in the page table and translation lookaside buffer (TLB).
Innovation Solution
Implementing a technique to coalesce mappings between contiguous virtual and physical pages, allowing the memory management unit to cache and translate addresses using coalesced mappings, reducing the number of page table entries (PTEs) needed and utilizing contiguous attributes to efficiently map virtual addresses to physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual PTEs are cached for each virtual page mapping, then address translation accuracy is improved, but cache memory usage and device complexity increase
Solution Approach 1:
The patent merges multiple contiguous PTEs into a single coalesced PTE entry that represents a range of virtual pages mapping to contiguous physical pages. Instead of caching individual PTEs for each virtual page, the system caches one coalesced PTE that covers multiple contiguous pages, thereby reducing cache memory usage while maintaining accurate address translation for all pages in the contiguous range.
2Measurement precision
If individual PTEs are updated when pages move between memory devices, then address translation accuracy is maintained, but communication traffic and processing time increase
Solution Approach 1:
When pages are moved between memory devices, the system updates the coalesced PTE entry that represents multiple contiguous pages simultaneously, rather than updating individual PTEs for each page. This merging approach maintains address translation accuracy for all pages in the range while significantly reducing the number of update operations and associated processing time.
3Measurement precision
If individual PTEs are updated when pages move between memory devices, then address translation accuracy is maintained, but communication traffic increases
Solution Approach 1:
The system merges multiple PTE updates into a single coalesced PTE update operation. When pages move between memory devices, the communication traffic required to update the page table is reduced because the system updates one coalesced entry representing multiple pages rather than individually updating each PTE, thereby maintaining address translation accuracy while reducing communication overhead.
Data Source
AI summary
A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced mappings are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can cache a single coalesced mapping and not all of them. The single cached coalesced mapping may be used to translate all of the virtual addresses to physical addresses for the corresponding contiguous memory space.