Coarse Fine Metal Interconnection Scheme for IC Speed
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Solution Overview
Problem
The miniaturization of Integrated Circuits leads to increased parasitic capacitance and resistance in metal interconnections, degrading chip performance, and existing methods for forming thick metal lines are costly and technically challenging due to stress and material costs.
Innovation Solution
A new interconnection scheme using an embossing process to form both coarse and fine line metal interconnections, where coarse metal lines are formed over fine line interconnections using selective electroplating, with a diffusion barrier to prevent penetration into fine line circuitry, and a passivation layer to protect against contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If blanket sputtering is used to create thick aluminum metal lines, then the metal lines can be formed, but the process becomes costly and creates stress issues
Solution Approach 1:
The patent introduces a seed layer as an intermediary between the substrate and the thick metal layer. This seed layer enables selective electroplating to occur only in desired regions, avoiding the stress and cost issues of blanket sputtering while achieving the required thick metal line formation
Solution Approach 2:
The patent applies local quality by using photolithography to pattern the seed layer, creating metal lines only in specific locations where needed. This localized approach eliminates the uniform stress distribution problem of blanket sputtering and reduces material costs by avoiding metal deposition in unnecessary areas
2Manufacturing precision
If blanket electroplating is used to form thick copper lines, then the metal lines can be formed, but large stress and high material cost occur
Solution Approach 1:
The patent uses a patterned seed layer as an intermediary that controls where electroplating occurs. This prevents blanket electroplating and its associated stress and material cost problems while still achieving thick copper line formation in the required locations
Solution Approach 2:
The patent implements local quality by restricting electroplating to specific patterned regions through the seed layer. This localized metal formation reduces material costs and minimizes stress by avoiding uniform thick metal deposition across the entire wafer
3Reliability
If wider metal lines are used to reduce resistance, then voltage drop is reduced, but capacitance of the wires increases
Solution Approach 1:
The patent segments the interconnection system into fine line interconnections for signal paths and coarse metal interconnections for power and ground buses. This segmentation allows optimization of each type: thin lines for signals (low capacitance) and thick lines for power (low resistance), resolving the contradiction between resistance and capacitance
Solution Approach 2:
The patent applies local quality by using different metal line dimensions in different locations based on functional requirements. Power and ground buses use wide thick lines to minimize voltage drop, while signal interconnections use narrower lines to minimize capacitance, achieving both goals simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances IC speed, reduces power consumption, and allows for the formation of thick metal lines up to 20 microns, achieving lower sheet resistance and improved performance for high-speed, low-power IC chips.
Implementation Method 1
A coarse metal interconnect structure is formed over the fine line metal interconnection structure by an embossing process
Data Source
AI summary
A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.