Coarse-SAR ADC Architecture With Offset Error Correction
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Solution Overview
Problem
Successive approximation register analog to digital converters (SAR ADCs) face challenges in high-speed applications due to inherent slowness and high dynamic power consumption, which is exacerbated by the need for error correction cycles, and combining SAR ADCs with coarse ADCs introduces complexity and area/power issues.
Innovation Solution
A SAR ADC system that incorporates a coarse ADC to resolve initial bits, followed by SAR ADC for fine resolution, with error correction using a predefined offset to simplify the process and reduce complexity, eliminating the need for additional capacitors and complex digital implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a SAR ADC operates at high frequency to achieve 100 MSPS throughput, then speed is improved, but dynamic power consumption increases proportionately
Solution Approach 1:
The patent divides the 10-bit conversion process into two segments: a coarse ADC that resolves the first 2 bits (requiring only 4 comparators) and a SAR ADC that resolves the remaining bits. This segmentation allows the SAR ADC to operate at lower frequency since it only needs to process 8 bits instead of 10, thereby reducing dynamic power consumption while maintaining 100 MSPS throughput
2Speed
If a coarse ADC is used to resolve first few bits, then SAR ADC speed requirements are relaxed, but device complexity increases
Solution Approach 1:
The patent merges the coarse ADC and SAR ADC into a unified conversion architecture where the coarse ADC output directly feeds the SAR ADC. The capacitor array is shared between both converters, and the conversion process is integrated such that the coarse conversion and fine conversion occur in a coordinated manner, reducing overall system complexity despite the dual-converter approach
3Measurement precision
If error correction cycles are added to SAR ADC, then measurement precision is improved, but speed decreases and dynamic power consumption increases
Solution Approach 1:
The patent performs error correction in advance by incorporating a predefined offset (0.5 LSB) during the coarse conversion phase. This preliminary error correction eliminates the need for subsequent error correction cycles, allowing the SAR ADC to complete its conversion in fewer steps and maintain high operating speed while achieving 10-bit precision
Data Source
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AI summary
In described examples, a successive approximation register analog to digital converter (SAR ADC) receives an input voltage (102) and multiple reference voltages (105). The SARADC (100) includes a charge sharing DAC (110). The charge sharing DAC (110) includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector (116) is coupled to the charge sharing DAC (110). The zero crossing detector (116) generates a digital output ( 118). A coarse ADC ( 122) receives the input voltage ( 102) and generates a coarse output (124). A predefined offset is added to a residue of the coarse ADC (122). A successive approximation register (SAR) state machine (120) is coupled to the coarse ADC (122) and the zero crossing detector (116) and generates multiple control signals (126). The control signals (126) operate the charge sharing DAC (110) in a sampling mode, an error-correction mode and a conversion mode.