Coaxial Grid Array Capacitor for IC Decoupling
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Solution Overview
Problem
The increasing operational frequencies and signal slew rates in ICs require additional decoupling and AC coupling capacitance at the IC package/PCB interface, which existing technologies often disrupt the wiring flow and design constraints, especially in breakout areas, leading to increased design complexity and potential electrical design requirement failures.
Innovation Solution
The implementation of grid array capacitors with an inner and secondary conductor in a coaxial orientation, surrounded by dielectric, which are physically and electrically connected to both the IC package and PCB, providing additional decoupling and AC coupling capacitance without disrupting the wiring flow, and can be manufactured by inserting dielectric and conductors into each other and applying solder paste for reflowing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional decoupling capacitors are added at the IC package/PCB interface, then additional decoupling and AC coupling capacitance is provided, but the wiring flow is disrupted and design complexity increases
Solution Approach 1:
The patent combines the capacitor structure with the existing solder column array by integrating capacitive elements between adjacent solder columns. This merging approach allows the capacitor to be formed within the existing interconnect structure without adding separate components that would disrupt wiring flow or increase design complexity.
Solution Approach 2:
The capacitor structure is nested within the existing solder column array footprint. The inner conductor is positioned within or between the solder columns, and the dielectric material is contained within the same vertical space, effectively nesting the capacitive element within the existing interconnect structure.
2Reliability
If more decoupling capacitance is added to meet high-frequency requirements, then electrical design requirements are met, but the breakout area becomes more congested
Solution Approach 1:
The patent transitions from a planar capacitor layout to a three-dimensional structure by forming capacitive elements vertically between the IC package and PCB. The inner conductor extends vertically through dielectric material, utilizing the vertical dimension to provide capacitance without occupying additional horizontal breakout area.
Solution Approach 2:
The capacitor structure is nested within the existing solder column array footprint. The inner conductor is positioned within or between the solder columns, and the dielectric material is contained within the same vertical space, effectively nesting the capacitive element within the existing interconnect structure.
3Reliability
If conventional capacitor structures are used, then decoupling function is provided, but additional series inductance is introduced
Solution Approach 1:
The patent extracts the harmful series inductance by eliminating the need for separate capacitor leads and traces. The inner conductor provides a direct vertical connection from the IC package through the capacitor structure to the PCB, removing the additional inductive paths that would be introduced by conventional capacitor mounting methods.
Solution Approach 2:
The patent combines the capacitor structure with the existing solder column array by integrating capacitive elements between adjacent solder columns. This merging approach allows the capacitor to be formed within the existing interconnect structure without adding separate components that would disrupt wiring flow or increase design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances PCB wiring flow, meets electrical design constraints without excessive design effort, and provides increased capacitance without additional series inductance, supporting AC coupling and power supply decoupling while maintaining the integrity of the existing columnar attach mechanism.
Implementation Method 1
an inner dielectric in a coaxial orientation to, and at least partially surrounding the inner conductor
Implementation Method 2
a secondary conductor in a coaxial orientation to, and at least partially surrounding the inner dielectric
Implementation Method 3
applying solder paste to opposing ends of the secondary conductor and to opposing ends of the inner conductor
Data Source
AI summary
A grid array capacitor can be used to physically and electrically couple an integrated circuit (IC) package to a printed circuit board (PCB). The grid array capacitor includes an inner conductor and an inner dielectric coaxially surrounding the inner conductor. A secondary conductor can be located to surround, in a coaxial orientation, the inner dielectric. Both the inner conductor and the secondary conductor can be electrically connected to the IC package and to the PCB. In certain applications, the structure of the inner conductor, inner dielectric, and secondary conductor can provide capacitance used to decouple electronic circuits.