Coaxial Solder Bump Support Structure for Wafer Warp Reduction
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Solution Overview
Problem
The formation of solder joints between semiconductor chips and substrates is hindered by shear stresses caused by thermal expansion mismatch, leading to tensile stress and potential cracking, particularly due to the use of thick protective insulator materials that increase wafer warp and bow, making it difficult to maintain specifications for subsequent processing operations.
Innovation Solution
A solder bump support structure is created with an inter-level dielectric layer, a pedestal member with a conductive material surrounded by a thicker insulation layer, and a capping under bump metal layer, utilizing excimer laser pulse technology for depth-specific etching to reduce the thickness of protective insulator material and minimize wafer warp and bow, while maintaining electrical contact and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick protective insulator material is used to mitigate CTE mismatch stresses, then stress protection is improved, but wafer warp and bow increase
Solution Approach 1:
The patent applies local quality by creating a non-uniform insulation layer thickness distribution. The insulation layer is thickest at the center of the chip where stress protection is most needed, and progressively thinner toward the edges. This localized variation in thickness provides stress mitigation exactly where the CTE mismatch generates highest stresses, while minimizing the overall warp and bow of the wafer by reducing material volume at locations where stress protection is less critical.
Solution Approach 2:
The patent changes the parameter of insulation layer thickness from a constant value to a spatially varying value. By transitioning from a uniform thick insulation layer to a graded thickness profile, the patent optimizes the balance between stress protection and wafer flatness. The thickness parameter is adjusted locally to achieve the desired mechanical performance without excessive warp and bow.
2Reliability
If uniform thick insulation layer is used for stress protection, then solder bump reliability is improved, but manufacturing precision deteriorates due to excessive warp and bow
Solution Approach 1:
The patent implements local quality by making the insulation layer thickness location-dependent. The thickness is optimized at each position on the chip based on the local stress requirements. This localized optimization ensures solder bump reliability where needed while maintaining wafer flatness for manufacturing precision by using thinner material at locations where it is less critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wafer warp and bow by half, allowing the use of more stressful protective insulator materials and improving the reliability of solder bump connections by reducing tensile stress and crack formation, while also simplifying the fabrication process with fewer required steps.
Implementation Method 1
utilizing excimer laser pulse technology for depth-specific etching to reduce the thickness of protective insulator material and minimize wafer warp and bow
Implementation Method 2
Because the substrate has a much larger coefficient of thermal expansion (CTE) than the chip, the substrate typically shrinks more than the chip during cooling to room temperature
Data Source
AI summary
A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.