Coaxial Via Laminate Interconnect for Inductance Reduction
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Solution Overview
Problem
Modern ASICs face performance issues due to high inductance in power supply and signal distribution networks, which affects signal isolation and increases cross-talk between signal paths.
Innovation Solution
A laminate interconnect structure with a coaxial via design, featuring a core material and additional conductive layers separated by non-conductive material, minimizes inductance by providing two electrical paths between the ASIC and the PCB while reducing the area used.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single via connections are used, then the structure is simple, but the loop inductance is high which negatively affects ASIC performance
Solution Approach 1:
The single via connection is segmented into two separate vias (first via and second via) that are spaced apart from each other. This segmentation creates multiple current paths between power and ground, effectively reducing the loop inductance while maintaining structural simplicity through the use of standard via fabrication processes
Solution Approach 2:
The patent transitions from a single-point via connection to a distributed via arrangement by spacing multiple vias apart along the laminate structure. This dimensional distribution creates a larger effective area for current flow, reducing inductance without requiring complex three-dimensional via structures
2Reliability
If multiple vias are spaced apart to reduce inductance, then the loop inductance decreases, but the area used increases
Solution Approach 1:
The via spacing is applied locally rather than uniformly across the entire laminate structure. The first and second vias are positioned at specific locations where inductance reduction is most beneficial, allowing inductance minimization in critical paths while conserving overall laminate area
Solution Approach 2:
The patent optimizes the spacing distance between vias to achieve the desired inductance reduction while minimizing area consumption. By carefully controlling the separation distance parameter, the design achieves effective inductance reduction without excessive area usage
Data Source
AI summary
A laminate interconnect structure includes a core material and at least one additional layer adjacent the core material, a first electrically conductive via formed in the core material, and a second electrically conductive via formed in the core material, coaxial with the first electrically conductive via and separated from the first electrically conductive via by a non-conductive material.