Capacitor Over Bit Line Fabrication Process Simplification
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Solution Overview
Problem
The complex process of fabricating capacitors in semiconductor memory devices, such as DRAM, requires multiple intricate steps, making it desirable to simplify the fabrication process while maintaining the necessary electrical connections and dielectric properties.
Innovation Solution
A method is introduced that simplifies the fabrication of a capacitor over a bit line by forming landing plug contacts, bit line contacts, and capacitor-terminal contacts in stages, using dielectric layers and metal plugs, with a focus on planarization and passivation to reduce the number of processing steps and enhance compatibility with semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-step fabrication process is used, then reliable electrical connections and dielectric properties are achieved, but the fabrication process becomes complex with many processing steps
Solution Approach 1:
The patent combines the formation of bit line contact, capacitor terminal contact, and landing plug contact into a single integrated process step. Multiple contacts are formed simultaneously through one set of photolithography and etching operations, eliminating the need for separate processing steps for each contact type. This merging approach maintains reliable electrical connections while significantly reducing fabrication process complexity.
Solution Approach 2:
The patent creates a universal contact formation process that serves multiple functions simultaneously. The same process structure and materials are used to form different types of contacts (bit line contact, capacitor terminal contact, landing plug contact), making the process multi-functional and adaptable to various connection requirements without needing separate specialized processes for each contact type.
2Reliability
If conventional multi-step fabrication process is used, then reliable electrical connections and dielectric properties are achieved, but the number of processing steps increases
Solution Approach 1:
The patent merges multiple contact formation operations into a single integrated process step. By forming bit line contacts, capacitor terminal contacts, and landing plug contacts simultaneously through one photolithography and etching cycle, the number of processing steps is reduced. This increases fabrication efficiency and productivity while maintaining the reliability of electrical connections through the unified process approach.
Solution Approach 2:
The patent performs preliminary preparation of contact openings and masking structures in advance, allowing multiple contact types to be formed in a single subsequent etching step. The contact opening definitions and mask patterns are prepared beforehand to enable simultaneous formation of different contacts, reducing the total number of processing steps and improving fabrication throughput while ensuring reliable connections.
Data Source
AI summary
A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then formed on the LPCs. Thereafter, a plurality of second contacts is formed on a first portions of the first contacts and a plurality of bit lines connecting a second portions of the first contacts is formed, simultaneously. An inter-layer dielectric (ILD) layer is formed on the substrate to cover the second contacts and the bit lines. Subsequently, a plurality of capacitors is formed in the ILD layer. Thus, the fabrication of the capacitor is simplified.