Chip-on-board package grounding pad structure for ESD noise reduction

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Solution Overview

Problem

Chip-on-board packages face challenges in reducing coupling between externally exposed terminals, leading to reliability issues due to electrostatic discharge (ESD) noise and increased capacitance.

Innovation Solution

Incorporating a grounding pad with a body portion, line portions, and conductive pads on a printed circuit board, where the line portions extend between conductive pads and have a narrower width than the pads, effectively shielding signal pads and reducing coupling capacitance by providing a path for ESD.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If terminals are arranged closely to achieve high density and miniaturization, then device size is reduced, but coupling between terminals increases leading to ESD noise and reliability issues

Engineering Contradiction:

Improvedevice sizeVSAvoidcoupling between terminals

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

A grounding pad structure is introduced as an intermediary element between adjacent conductive pads. The grounding pad includes a body portion and line portions that extend between the pads, creating a shielding effect that reduces coupling capacitance. This mediator provides a reference potential that isolates the signal pads from each other, thereby reducing ESD noise while allowing the terminals to remain closely spaced for high density.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If grounding pad is added to reduce coupling capacitance, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvecoupling capacitance reductionVSAvoidgrounding pad structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The grounding pad is merged with the existing pad structure by using the same conductive material layer and forming process. The body portion and line portions are integrated into the PCB fabrication process, eliminating the need for separate grounding structures. This combining approach reduces manufacturing steps and overall device complexity while maintaining the ESD protection and coupling reduction benefits.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces coupling capacitance between adjacent conductive pads by up to 40%, minimizing ESD noise and enhancing the reliability of chip-on-board packages.

Implementation Method 1

the line portion may extend so as to shield the entire second side

Methodology Applied

Scientific EffectElectrostatic shielding: Faraday Cage

Implementation Method 2

capable of preventing or reducing coupling between terminals that may be externally exposed

Methodology Applied

Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentUS8143713B2Chip-on-board package

Publication Date: 2012.03.27 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a chip-on-board package. The chip-on-board package may include a board, a grounding pad on a first surface of the board, the grounding pad including a body portion and at least one line portion, and at least two conductive pads on the first surface, the at least two conductive pads being arranged adjacent to the body portion. The at least one line portion may extend between the at least two conductive pads and the at least one line portion may have a narrower width than the at least two conductive pads.