Cobalt-Capped Copper Access Lines for 3D Memory
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Solution Overview
Problem
Three-dimensional memory devices face challenges with high sheet resistances and parasitic capacitances in access lines, such as word lines and bit lines, which degrade performance due to IR drop and RC delay, and pitch scaling increases parasitic capacitances, necessitating improved materials and fabrication methods.
Innovation Solution
The use of cobalt-capped copper access lines with self-aligned cobalt access line caps reduces resistance without significant increases in processing cost, employing selective cobalt deposition and self-aligned damascene trench formation to form low-resistance access lines in a three-dimensional memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional copper access lines are used in three-dimensional memory devices, then manufacturing cost is low, but sheet resistance is high causing performance degradation
Solution Approach 1:
The patent uses composite materials by combining copper (for low resistance) with cobalt capping layers (for protection and controlled growth). The copper fill portion provides excellent electrical conductivity while the cobalt cap liner prevents oxidation and enables selective growth processes, creating a composite structure that optimizes both electrical performance and manufacturability
2Productivity
If access line pitch is scaled down to increase memory density, then device capacity increases, but parasitic capacitance increases causing RC delay
Solution Approach 1:
The patent changes material parameters by introducing cobalt capping layers with specific thicknesses and growth characteristics. The selective cobalt growth on copper surfaces modifies the electrical and physical parameters of the access lines, reducing parasitic capacitance effects while maintaining low resistance, thereby enabling tighter pitch scaling
3Quantity of substance
If cobalt cap liner is grown from copper fill portion, then sheet resistance is reduced, but processing complexity increases
Solution Approach 1:
The patent employs self-service through selective growth mechanisms where the cobalt cap liner automatically grows only on exposed copper surfaces and not on dielectric materials. This self-selective process eliminates the need for additional masking steps or complex alignment procedures, reducing processing complexity while achieving the desired low-resistance structure
4Duration of action of stationary object
If conventional electroplating is used for copper fill, then processing is simple, but electromigration failure lifetime is short
Solution Approach 1:
The patent applies preliminary action by depositing cobalt cap liners on the copper fill portions before completing the copper electroplating process. This preliminary cobalt capping protects the copper from oxidation and reduces electromigration effects during subsequent processing steps, extending the device lifetime without significantly complicating the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces sheet resistances by 18% to 57% at different pitch nodes and significantly enhances electromigration failure lifetime, while reducing parasitic capacitance and processing costs, enabling more efficient and reliable three-dimensional memory devices.
Implementation Method 1
selectively growing a first cobalt-containing cap liner from physically exposed surfaces of the first copper-containing fill portion while suppressing growth of cobalt from physically exposed surfaces of the first dielectric rails
Data Source
AI summary
A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.