Metal Cap on Cobalt Layer for IC Source Drain
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Solution Overview
Problem
In integrated circuit (IC) manufacturing, particularly in FEOL processing, materials like cobalt are challenging to incorporate due to erosion and contamination risks during chemical mechanical planarization (CMP), leading to non-compliance with design requirements and potential electrical shorting issues.
Innovation Solution
A method involving forming a semiconductor fin with a cobalt layer protected by a metal cap, where the cobalt layer is selectively etched and recessed beneath the gate structure, ensuring the cobalt residue is exposed only after forming metal caps and overlying gate metals, thus preventing erosion and contamination during subsequent processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If cobalt layer is exposed during CMP processing, then planarization can be performed, but erosion and contamination of the cobalt layer occurs
Solution Approach 1:
An insulator cap is introduced as an intermediary protective layer between the cobalt layer and the CMP slurry. The cap allows CMP processing to proceed on its surface while preventing direct contact between the slurry and cobalt, thus eliminating erosion and contamination. After processing, the cap is removed to reveal the protected cobalt layer.
Solution Approach 2:
The insulator cap is formed preliminarily before CMP processing to protect the cobalt layer. This preliminary protective action ensures that when CMP is performed, the cobalt layer is already shielded from harmful slurry contact, preventing erosion and contamination before they can occur.
2Reliability
If cobalt layer is used in FEOL structures, then desired electrical properties are achieved, but design rule compliance becomes difficult due to erosion
Solution Approach 1:
The insulator cap serves as a mediator that protects the cobalt layer during subsequent processing steps. By preventing erosion, the cap ensures that the cobalt layer maintains its intended dimensions and position, thereby ensuring compliance with design rules while preserving the desired electrical properties.
Solution Approach 2:
The insulator cap provides beforehand cushioning or protection against process-induced erosion. This prior protective measure ensures that even during aggressive CMP or etching processes, the cobalt layer dimensions remain controlled and compliant with design specifications.
3Manufacturing precision
If cobalt layer is exposed to CMP slurry, then material can be removed for planarization, but unintended erosion and material migration occur
Solution Approach 1:
The insulator cap acts as an intermediary barrier that allows controlled material removal via CMP on the cap surface itself, while preventing the slurry from contacting and eroding the cobalt layer. This eliminates unintended material migration from the cobalt layer during planarization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects the cobalt layer from erosion and contamination, ensuring compliance with design requirements and preventing electrical shorting, while allowing for the successful integration of cobalt in transistor structures without compromising other processing steps.
Implementation Method 1
a metal cap on the Co layer
Implementation Method 2
selectively etching the bulk Co layer to form a Co layer on the semiconductor fin, wherein the selective etching removes the bulk Co layer from the second opening and recesses the bulk Co layer below an upper surface of the gate structure
Data Source
AI summary
The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.