Metal Gate Electrodes Using Cobalt Layers to Cut Gate Resistivity

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Solution Overview

Problem

MOS devices with polysilicon gate electrodes suffer from carrier depletion effects, leading to increased effective gate dielectric thickness and difficulty in creating an inversion layer, and tungsten nucleation layers have high resistivity, impacting transistor performance, especially as devices are scaled down.

Innovation Solution

The formation of metal gate electrodes with a cobalt or metal silicide layer, which has low resistivity and good adhesion to underlying layers, replacing tungsten nucleation layers to improve transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If tungsten nucleation layer is used to improve adhesion, then adhesion to underlying layers is improved, but resistivity increases significantly

Engineering Contradiction:
ImproveadhesionVSAvoidresistivity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent uses a composite metal gate structure consisting of multiple layers including tungsten nucleation layer, cobalt layer, and tungsten layer. This composite structure combines the adhesion benefits of tungsten nucleation layer with the low resistivity of cobalt and tungsten, resolving the contradiction between adhesion and resistivity.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies different materials with different properties to different locations in the gate structure. The tungsten nucleation layer is used only where adhesion is needed (at the interface with underlying layers), while cobalt and tungsten layers are used where low resistivity is needed, achieving local optimization of properties.

Inventive Principle:
Principle #3Local quality

2Productivity

If device size is scaled down to increase productivity, then transistor density increases, but resistivity of nucleation layer significantly impacts performance

Engineering Contradiction:
Improvetransistor densityVSAvoidtransistor performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the material composition and layer thickness parameters of the metal gate structure. By optimizing the thickness of each layer (nucleation layer, cobalt layer, tungsten layer) and their material properties, the patent achieves low overall resistivity that maintains transistor performance even as device dimensions are scaled down for higher density.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If polysilicon gate electrode is used to adjust work function, then work function can be tuned to band-edge, but carrier depletion effect occurs

Engineering Contradiction:
Improvework function adjustmentVSAvoidinversion layer formation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent replaces polysilicon gate electrode with metal gate electrode structure. The metal gate eliminates the carrier depletion effect inherent in polysilicon while maintaining the ability to achieve appropriate work functions through material selection and layer composition, thus improving inversion layer formation.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of cobalt or metal silicide layers reduces resistivity and enhances adhesion, addressing carrier depletion and scaling issues in MOS devices by improving the performance of transistors, particularly in FinFETs.

Implementation Method 1

depositing a metal-containing layer over and in contact with the metal nitride barrier layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

which has low resistivity and good adhesion to underlying layers

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS11810819B2Metal gates of transistors having reduced resistivity
Publication Date: 2023.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11810819B2 patent drawing
  • US11810819B2 patent drawing
  • US11810819B2 patent drawing

AI summary

A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.