Cobalt Reflow Metallization for Interconnect RC Delay

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Solution Overview

Problem

As integrated circuit dimensions shrink, conventional lithography faces challenges in creating smaller structures, leading to increased resistance-capacitance (RC) delay due to higher copper resistivity, which affects signal speed and overall circuit performance.

Innovation Solution

A method involving a multiple fill metallization process using a ruthenium and cobalt layer combination, where a cobalt layer is reflowed to fill features, reducing aspect ratios and improving metal fill properties, electromigration resistance, and reliability of interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If copper interconnect dimensions are reduced to improve circuit integration density, then more circuit features can be packaged closer together, but copper resistivity increases causing increased RC delay

Engineering Contradiction:
Improvecircuit integration densityVSAvoidRC delay
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent uses a composite interconnect structure consisting of multiple materials: copper base layer, ruthenium layer, and cobalt layer. This composite structure combines the advantages of each material - copper provides high conductivity, while ruthenium and cobalt layers reduce resistivity and prevent copper migration, thereby maintaining low RC delay at reduced dimensions

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the material composition parameters of the interconnect structure by introducing ruthenium and cobalt layers. This parameter change modifies the electrical properties (resistivity) and structural properties (migration resistance) of the interconnect, enabling continued scaling without proportionate increase in RC delay

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If conventional lithography is used to create smaller structures, then manufacturing process is simple, but manufacturing precision deteriorates as dimensions shrink below lithography capabilities

Engineering Contradiction:
Improvelithography process simplicityVSAvoidfeature dimension precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the interconnect formation process into multiple distinct steps: copper deposition, ruthenium layer deposition, and cobalt layer deposition. Each step can be optimized independently with appropriate deposition techniques, allowing precise control of each layer's thickness and properties to achieve the required manufacturing precision for scaled features

Inventive Principle:
Principle #1Segmentation

3Productivity

If copper interconnects are used at reduced dimensions, then circuit packaging density improves, but electromigration resistance deteriorates due to higher current density

Engineering Contradiction:
Improvecircuit packaging densityVSAvoidelectromigration resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The ruthenium and cobalt layers act as intermediary protective layers between the copper conductors and the environment. These layers prevent copper surface migration and electromigration by providing a stable diffusion barrier, thereby maintaining electromigration resistance even as copper interconnect dimensions are reduced for higher packaging density

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The ruthenium/cobalt combination effectively reduces RC delays, enhances metal fill properties, and improves the reliability of interconnects by providing better lattice matching and reduced copper surface migration, thus improving the performance of aggressively scaled features.

Implementation Method 1

Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 2

A thermal anneal reflows the cobalt layer to fill a second portion of the set of features

Methodology Applied
Scientific EffectThermal anneal: Annealing

Data Source

PatentUS10236257B2Cobalt top layer advanced metallization for interconnects
Publication Date: 2019.03.19 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10236257B2 patent drawing
  • US10236257B2 patent drawing
  • US10236257B2 patent drawing

AI summary

A method for constructing an advance conductor structure is described. A pattern is provided in a dielectric layer in which a set of features are patterned for a set of metal conductor structures. An adhesion promoting layer is created disposed over the patterned dielectric. A metal layer is deposited to fill a first portion of the set of features disposed the adhesion promoting layer. A ruthenium layer is deposited disposed over the metal layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer. A thermal anneal reflows the cobalt layer to fill a second portion of the set of features.