Cobalt Silicide Layer Stack for Defect-Free IC Contacts

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Solution Overview

Problem

Integrated circuit production methods often result in defects and dislocations during the stacking of layers, which can impair the quality of electrical connections and lead to delamination issues.

Innovation Solution

A method involving the deposition of a first metallic layer, a protective titanium nitride layer, and an additional stress-balancing layer to prevent lattice defects, followed by heat treatments to form cobalt silicide with different stoichiometries, ensuring defect-free and dislocation-free integrated circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If layers are stacked to prevent making holes at interfaces, then delamination risk is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvedelamination preventionVSAvoidlayer stacking complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the additional layer on the protective layer before the heat treatment step. This additional layer is pre-positioned to compensate for stress effects that will occur during subsequent processing, preventing defects before they happen rather than correcting them afterward.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The additional layer acts as an intermediary between the protective layer and the first metallic layer. It mediates the stress effects between layers with different atomic dimensions, distributing and balancing the directional stresses to prevent both delamination and lattice defects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If heat treatment is performed to form cobalt silicide, then electrical connection quality is improved, but lattice defects and dislocations occur

Engineering Contradiction:
Improveelectrical connection qualityVSAvoidlattice defect prevention
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary anti-action by introducing the additional layer that creates opposing directional stress to counteract the stress-induced lattice defects. This layer preemptively balances the stresses that would otherwise cause dislocations during heat treatment, allowing high-quality electrical connections without lattice defects.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent changes the stress parameter by adding a layer with different mechanical properties. This additional layer modifies the overall stress state in the stack, transforming the harmful compressive or tensile stresses into a balanced state that prevents lattice defects while maintaining the heat treatment benefits.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively eliminates defects and dislocations, ensuring high-quality electrical connections and preventing delamination, with the additional layer compensating for stress effects between chemical constituents, resulting in a defect-free integrated circuit.

Implementation Method 1

an additional layer composed of a main chemical constituent different from or equivalent to, or of equivalent size to, the main chemical constituent of the first layer is further deposited on the protective layer to compensate for stress effects between chemical constituents

Methodology Applied
Scientific EffectStress balancing: Stress Relaxation

Implementation Method 2

a heat treatment (heating) is carried out, which is the step RTA1. This heat treatment can be of the order of 500° C., but at least 350° C. to modify at least the first layer here from cobalt to cobalt silicide

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Implementation Method 3

a further heat treatment of up to 750° C. to convert the cobalt silicide 2′′′ to a cobalt atom bonded to two silicon atoms (CoSi2), with some of the silicon diffused in the first cobalt layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 4

This cobalt layer can be deposited by PVD deposition

Methodology Applied
Scientific EffectPVD deposition: Physical Vapour Deposition

Data Source

PatentUS20240170298A1Method for producing an integrated circuit to remedy defects or dislocations
Publication Date: 2024.05.23 EM MICROELECTRONIC-MARIN
  • US20240170298A1 patent drawing
  • US20240170298A1 patent drawing
  • US20240170298A1 patent drawing

AI summary

A method to produce an integrated circuit including depositing a first layer of a metallic chemical constituent on a silicon substrate. A protective layer including a main chemical constituent different from the main chemical constituent of the first layer is then deposited on this first layer. An additional layer is deposited on the protective layer and includes a main chemical constituent different from, equivalent to or of equivalent size to the main chemical constituent of the first layer. A heat treatment operation is carried out at a first temperature to generate a silicide including the main constituent of the first layer and silicon according to a first stoichiometry. In a subsequent step, the additional layer and the protective layer are removed. In another step, a further heat treatment operation is carried out at a temperature greater than the first temperature in order to change the stoichiometry of the previously created silicide.