Chip-on-Chip Package Layout for Shorter High-Speed Signal Paths
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Solution Overview
Problem
Chip-on-chip (CoC) packages face challenges with high resistance and long transmission paths due to wire bonding, limiting high-speed signal transmission capabilities, especially in applications requiring data rates of 100 Gbit/s, 400 Gbit/s, or 1.6 Tbit/s, and silicon photonics integration with electronic and photonic ICs.
Innovation Solution
The electronic device package employs conductive structures such as solder-free conductive pillars to connect semiconductor dies and circuit layers, reducing transmission path length and impedance, and incorporates a redistribution trace layer for fan-out structures to enhance electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect stacked electronic components, then electrical communication between components is achieved, but high resistance and long transmission path are introduced
Solution Approach 1:
The patent extracts and eliminates the wire bonding interconnection method from the stacked package structure. Instead of using wire bonds to connect the first and second electronic components, the invention directly bonds the components together, removing the intermediate wire bonding step that causes long transmission paths and high resistance.
Solution Approach 2:
The patent introduces an intermediary approach by using a eutectic bonding process with a controlled bonding temperature range (200°C to 400°C) that enables direct bonding between components without wire bonds. This intermediary bonding process allows the components to fuse directly, eliminating the need for wire bonds while maintaining reliable electrical connection.
2Productivity
If wire bonding is used for electrical communication, then components can be connected, but high impedance prevents high speed data rate realization
Solution Approach 1:
The patent removes the wire bonding intermediary that causes high impedance. By directly bonding the electronic components together, the transmission path becomes much shorter and has lower impedance, enabling high-speed data transmission at rates of 100 Gbit/s, 400 Gbit/s, or 1.6 Tbit/s.
Solution Approach 2:
The patent changes the bonding temperature parameter to a eutectic range (200°C to 400°C) that enables direct bonding without wire bonds. This parameter change allows the formation of low-impedance direct connections between components, supporting high-speed data transmission capabilities.
3Reliability
If conventional bonding processes are used, then components can be joined, but signal integrity deteriorates due to long transmission paths
Solution Approach 1:
The patent extracts and eliminates the conventional wire bonding process from the stacked package structure. By directly bonding the first and second electronic components together through eutectic bonding, the transmission path length is dramatically reduced, improving signal integrity for high-frequency applications.
Solution Approach 2:
The patent replaces the mechanical wire bonding system with a thermal eutectic bonding process. Instead of using wire bonds that extend the transmission path, the components are bonded directly through controlled heating to eutectic temperatures, creating short, low-inductance connections that maintain signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high-speed signal transmission exceeding 400 Gbit/s by minimizing signal integrity issues and impedance, enabling efficient data transfer between electronic and photonic ICs.
Implementation Method 1
The first conductive structures are disposed between a first region of the second semiconductor die and the second semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die
Implementation Method 2
The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die
Data Source
AI summary
An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.