Code Conversion Apparatus for Array of Structures Layout Optimization
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Solution Overview
Problem
The use of a Structure of Arrays (SoA) layout in data definitions for SIMD operations leads to decreased cache efficiency and processing performance due to non-local access patterns, as not all elements are stored in cache memory, resulting in TLB errors and resource inefficiencies.
Innovation Solution
A code conversion apparatus that transforms data definitions and operations from a Structure of Arrays (SoA) layout to an Array of Structures (AoS) layout, optimizing SIMD instructions to improve cache locality and reduce TLB errors by rearranging data for better access patterns, using AoS-dedicated instructions or existing instructions for efficient SIMD extension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a Structure of Arrays (SoA) layout is used for SIMD operations, then SIMD extension and parallel processing capability are improved, but cache efficiency and processing performance deteriorate due to non-local access patterns
Solution Approach 1:
The patent inverts the conventional SoA data layout approach by adopting Array of Structures (AoS) layout instead. This inversion changes the access pattern from non-local to local, allowing elements of the same structure to be accessed sequentially in memory, thereby improving cache efficiency while maintaining SIMD parallel processing capability through vertical extension
2Speed
If SoA layout is used with SIMD instructions, then operation speed on multiple data elements is improved, but TLB errors and resource inefficiencies increase due to decreased data locality
Solution Approach 1:
The patent transitions from horizontal SIMD extension (processing multiple elements of the same array in parallel) to vertical SIMD extension (processing multiple elements of different arrays in parallel through AoS layout). This dimensional change in data organization allows elements to be stored contiguously in memory while enabling parallel operations across different array types, thereby maintaining high operation speed and reducing TLB errors
Data Source
AI summary
A code conversion apparatus includes a memory and a processor coupled to the memory. The memory is configured to store therein a first code including a first data definition of a plurality of arrays, a first operation for the plurality of arrays, and a second data definition of an array indicating a result of the first operation. The processor is configured to convert the first data definition and the second data definition included in the first code into a data definition of an array of structures. The processor is configured to convert the first operation included in the first code into a second operation for the array of structures. The processor is configured to generate a second code including a predetermined instruction to perform the second operation on different pieces of data of the plurality of arrays in parallel with one another.


