Code Sequencer Offloads Processor Load for SDN Flexibility
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Solution Overview
Problem
Modern telecommunications networks face challenges due to proprietary hardware that requires frequent reconfiguration and maintenance, leading to inflexibility and inefficiency in providing dynamic services, especially with the increasing demands of Software Defined Networking (SDN) and Network Functions Virtualization (NFV) that necessitate improved data plane processing performance.
Innovation Solution
A code sequencer is introduced that executes predefined and hardcoded sequences as a thread using run-to-completion scheduling, offloading frequent tasks from the main processor cores and leveraging logic circuitry and accelerators to improve system performance by reducing the load on the primary processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If proprietary hardware is used for network functions, then network services can be provided, but the system becomes inflexible and requires frequent reconfiguration and maintenance
Solution Approach 1:
The patent replaces hardware-based network functions with software-based virtualized network functions that run on general-purpose processors. This substitution eliminates the need for physical reconfiguration of hardware appliances and enables flexible service deployment through software configuration, directly resolving the contradiction between adaptability and device complexity
Solution Approach 2:
The patent implements a universal processing platform that can execute multiple different network functions through software. Instead of dedicated hardware for each function, a single processor system can perform routing, switching, firewall, and other network functions by loading different software modules, achieving multi-functionality without increasing hardware complexity
2Adaptability or versatility
If virtualized network functions are implemented to increase flexibility, then service dynamism is improved, but data processing demands increase significantly
Solution Approach 1:
The patent segments the processing workload by separating control plane functions from data plane functions. The control plane handles configuration and management, while the data plane is optimized for high-speed packet processing. This segmentation allows each part to be optimized independently, maintaining service dynamism while improving data processing productivity
Solution Approach 2:
The patent introduces an intermediary layer (the code sequencer and instruction execution mechanism) that mediates between the virtualized network functions and the underlying processor. This intermediary optimizes the execution path by pre-compiling and caching instruction sequences, reducing the processing overhead and improving data plane performance without sacrificing service flexibility
3Adaptability or versatility
If frequent reconfiguration and on-site installation of new equipment is performed, then new services can be launched, but maintenance requirements and floor space needs increase
Solution Approach 1:
The patent uses software copies to deploy network functions instead of physical equipment copies. Virtual network function instances can be rapidly copied and deployed across the network infrastructure through software replication, eliminating the need for physical installation and reducing maintenance complexity while maintaining full service deployment capability
Solution Approach 2:
The patent implements dynamic service deployment where network functions can be instantiated, moved, scaled, and terminated on-demand through software control. This dynamic approach replaces static hardware installations, enabling new services to be launched without physical reconfiguration and significantly reducing maintenance requirements
Data Source
AI summary
Instruction code is executed in a central processing unit of a network computing device. Besides the central processing unit the device is provided with a code sequencer operative to execute predefined instruction sequences. The code sequencer is invoked by a trigger instruction in the instruction code, which is encountered by the central processing unit. Responsively to its invocations the code sequencer executes the predefined instruction sequences.


