Code-Table Memory Cell Mapping for Multi-Bit Storage Efficiency
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Solution Overview
Problem
As the number of data bits stored in a memory cell increases, the efficiency of memory cells decreases, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A memory device is designed to divide and store data bits in multiple memory cells using a code table that maps data patterns to code patterns, employing encoding and inverting operations to optimize storage and retrieval processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of data bits stored in a memory cell increases, then the storage density improves, but the efficiency of memory cells decreases
Solution Approach 1:
The patent divides the data bits into multiple groups and distributes them across multiple memory cells. Specifically, it separates data bits into first data bits and second data bits, storing them in different memory cells with different encoding schemes. This segmentation allows each memory cell to operate at optimal efficiency while collectively achieving high storage density.
Solution Approach 2:
The patent applies different encoding schemes to different memory cells based on their specific roles. First memory cells store first data bits with a first encoding scheme, while second memory cells store second data bits with a second encoding scheme. This local differentiation optimizes the performance of each memory cell for its specific storage requirements.
2Quantity of substance
If the number of states of memory cells increases, then the storage capacity improves, but the complexity of operations increases
Solution Approach 1:
The patent segments the high-order data bits into multiple groups, each stored in separate memory cells with distinct states. This segmentation reduces the complexity of operations on individual cells while maintaining high overall storage capacity through the combined states of multiple cells.
Solution Approach 2:
The patent inverts the conventional approach by not storing all high-order bits in a single cell with multiple states, but rather distributing them across multiple cells. This inversion simplifies the operation logic while achieving the same storage capacity through a different organizational structure.
3Device complexity
If data bits are stored in fewer memory cells, then the device complexity decreases, but the efficiency of data storage and retrieval decreases
Solution Approach 1:
The patent segments data bits into multiple groups and distributes them across multiple memory cells, which increases the number of cells but optimizes the storage and retrieval efficiency. Each memory cell handles a specific portion of data with optimized encoding, improving overall system performance.
Solution Approach 2:
The patent changes the encoding parameters for different memory cells based on the data bits they store. By adjusting encoding schemes and other parameters for each memory cell, the system optimizes storage and retrieval efficiency despite using multiple cells.
Data Source
AI summary
The present technology relates to a semiconductor device. According to the present technology, a memory device capable of dividing and storing a plurality of data bits in a plurality of memory cells may include a plurality of memory cells each configured to have a state among a plurality of states, a code table generator configured to generate, based on a plurality of data bits, a code table indicating the plurality of states as code patterns formed by parts of the data bits, the parts corresponding to the respective memory cells, and an internal operation controller configured to divide and store a plurality of target data bits in the plurality of memory cells based on the code table during a program operation.