Codec Module Segmentation for Variable-Bit Image Processing
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Solution Overview
Problem
Existing image processing systems face challenges in efficiently processing variable-bit image signals, particularly in managing and transmitting multi-bit pixel data between processors, which can lead to inefficient bandwidth usage and image distortion.
Innovation Solution
The proposed solution involves an image processor that utilizes a codec module to encode or decode images from a CMOS image sensor, with a memory controller managing the storage and access of pixel data in a System-on-Chip (SoC). This system divides pixel data into more significant bits and less significant bits, storing and accessing them separately to optimize data transmission and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If variable-bit image signals are transmitted between processors using standard bus interfaces, then image processing can be performed, but bandwidth usage becomes inefficient and image distortion may occur
Solution Approach 1:
The patent segments pixel data into two distinct parts: MSB (most significant bits) and LSB (least significant bits). These segmented data parts are transmitted through separate pathways - MSB through a first bus interface and LSB through a second bus interface. This segmentation allows independent optimization of transmission channels for different data components, resolving the bandwidth efficiency problem by preventing data loss and distortion that occurs when variable-bit signals are transmitted as unified blocks through standard interfaces.
2Reliability
If all bits of pixel data are transmitted through a single bus interface, then data integrity can be maintained, but bandwidth resources are wasted due to variable bit requirements
Solution Approach 1:
Pixel data is divided into MSB and LSB components that are transmitted through separate bus interfaces. The MSB, which contains critical image information, is transmitted through a first bus interface with guaranteed data integrity. The LSB, containing less critical detail information, is transmitted through a second bus interface. This segmentation ensures data integrity for essential components while optimizing bandwidth consumption by allowing flexible transmission of less critical data.
Solution Approach 2:
Different transmission quality levels are applied to different parts of pixel data based on their importance. The MSB transmission path is designed with higher reliability requirements and dedicated resources, while the LSB transmission path can utilize available bandwidth more flexibly. This local quality differentiation maintains overall data integrity while optimizing total bandwidth usage, as critical data receives priority treatment while non-critical data fills remaining bandwidth capacity.
Data Source
AI summary
A system on a chip may include a codec module configured to receive an image including a plurality of first pixel data and output a plurality of second pixel data through a system bus. The codec module comprises at least one (M+N) bit logic circuit including M bit logic and N bit logic. The codec module is configured to operate in a first mode where the (M+N) bit logic circuit performs a dithering operation on the first pixel data of (M+N) bits and generates the second pixel data including at least M bits. The codec module is configured to operate in a second mode where the M-bit logic selectively operates and outputs the second pixel data of M bits.