Coded Memory Architecture for Multi-Core Bank Conflict Reduction
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Solution Overview
Problem
Current multi-core computer architectures experience increased latency due to bank conflicts when multiple cores request access to the same memory bank, leading to sequential serving of requests and longer wait times for some cores.
Innovation Solution
The implementation of a system with additional coded banks that store a coded version of data from memory banks, allowing the access scheduler to parallelize memory requests and reduce bank conflicts by utilizing these coded banks to serve read and write operations efficiently, while maintaining a status memory to track data freshness between memory and coded banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple cores request access to the same memory bank, then the memory controller serves requests sequentially through bank queues, but this increases latency and creates bank conflicts
Solution Approach 1:
The memory system is segmented into regular memory banks and coded memory banks. The coded banks store encoded versions of data from regular banks, allowing the system to serve read requests from either regular banks or coded banks depending on availability, thereby reducing bank conflicts and latency while maintaining data correctness through decoding operations.
Solution Approach 2:
The invention creates coded copies of data from regular memory banks and stores them in coded memory banks. These coded copies serve as alternative sources for satisfying read requests, reducing the need for sequential access to the same regular bank and thereby decreasing latency and bank conflicts.
2Device complexity
If the memory controller uses traditional bank queues to manage requests, then it maintains simple structure, but it experiences increased latency due to sequential serving of requests
Solution Approach 1:
The memory controller is segmented into multiple independent components: regular memory banks, coded memory banks, and multiple bank queues (including a coded bank queue). This segmentation allows parallel operation of different bank types, increasing memory access speed while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The memory controller is enhanced with multi-functionality by adding coded bank queues that can handle both regular and coded bank requests. The access scheduler can selectively serve requests from regular banks or coded banks based on queue status and conflict detection, improving productivity while maintaining a unified control structure.
3Productivity
If the system adds coded banks to reduce bank conflicts, then memory access speed increases, but device complexity increases due to additional memory structures
Solution Approach 1:
The memory architecture is segmented into regular memory banks and coded memory banks, each serving specific functions. This segmentation allows the system to distribute access patterns across different bank types, reducing conflicts and improving speed while maintaining organized, manageable complexity through clear functional separation.
Solution Approach 2:
Coded copies of data are created and stored in dedicated coded memory banks. This copying approach enables the system to serve requests from alternative locations, reducing bank conflicts and improving access speed. The complexity is managed by organizing coded banks as distinct structures with clear relationships to regular banks.
4Device complexity
If the access scheduler serves requests sequentially from bank queues, then it maintains simple control logic, but latency increases due to wait times for some cores
Solution Approach 1:
The control logic is segmented into multiple bank queues (regular bank queues and coded bank queue) that operate semi-independently. The access scheduler can select from multiple queues based on simple criteria such as queue depth and conflict status, reducing core wait times while maintaining manageable control logic through modular queue management.
Solution Approach 2:
The access scheduler implements dynamic selection among multiple bank queues based on real-time conditions such as queue status, conflict detection, and data freshness. This dynamic approach allows the system to adapt to varying access patterns, reducing latency and wait times while maintaining simple control logic through rule-based decision making.
Data Source
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AI summary
A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. The method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.