Coded to Raster Format Conversion Buffer Architecture
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Solution Overview
Problem
Existing circuit designs for converting pixel data between coded and raster formats face challenges due to substantial memory requirements and latency issues, particularly in field programmable gate arrays with limited on-chip memory resources, as they rely on large line buffers for chrominance subsampling.
Innovation Solution
The implementation of a buffer architecture with strided raster-scan techniques and a demultiplexer/multiplexer circuit arrangement that reduces memory requirements by up to 90% while maintaining high throughput, using a first and second buffer configured for storage of component blocks in coded and raster scan orders respectively, and enabling efficient data flushing in response to completed sets of blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large line buffers are used for chrominance subsampling, then conversion between coded and raster formats can be achieved, but hardware memory requirements become substantial
Solution Approach 1:
The patent divides the large line buffer into multiple smaller buffers organized in a bank structure. Instead of requiring one large buffer to hold all pixel data, the system segments memory into multiple banks that can be accessed in an interleaved manner, reducing the peak memory requirement while maintaining the same functional capability for chrominance subsampling.
Solution Approach 2:
The patent introduces a temporal dimension to the memory access pattern by using buffer banks with staggered read/write operations. Data is processed in a round-robin fashion across multiple buffer banks, allowing the system to achieve the same conversion capability with smaller individual buffer sizes by utilizing time-multiplexed access patterns.
2Adaptability or versatility
If separate line buffers are provided for U and V components, then chrominance subsampling is supported, but additional memory resources are required
Solution Approach 1:
The patent merges the storage of U and V chrominance components into a shared buffer structure. Instead of providing completely separate line buffers for each chrominance component, the system uses a unified buffer architecture that can store and manage both U and V data efficiently, reducing redundant memory allocation while maintaining full chrominance subsampling functionality.
Solution Approach 2:
The buffer architecture is designed to be universal and multi-functional, capable of storing luma and chrominance data, as well as supporting different chrominance subsampling formats (such as 4:2:0, 4:2:2). This universal buffer structure eliminates the need for dedicated separate buffers for each component type, optimizing memory resource utilization.
3Productivity
If large bursts are transmitted from line buffers, then data can be flushed efficiently, but latency increases
Solution Approach 1:
The patent implements periodic action through round-robin data flushing across multiple buffer banks. Instead of transmitting all data in one large burst from a single buffer, the system periodically flushes data from different buffer banks in an interleaved manner, breaking up large latency-inducing bursts into smaller, more frequent transmissions that maintain throughput while reducing latency.
Solution Approach 2:
The buffer management system dynamically switches between different buffer banks based on data availability and processing stage. This dynamic allocation and switching of buffer resources allows the system to optimize the balance between throughput and latency, adapting the flush pattern to current operational conditions rather than using fixed large bursts.
Data Source
AI summary
Disclosed approaches for converting between block coded format and raster format include buffers for first type component blocks and second type component blocks of a frame. The buffers are sized less than the width of the frame. A demultiplexer circuit is configured to input the first type component blocks and the second type component blocks in coded block order, and enable storage of the first type component blocks in the first buffer and of the second type component blocks in the second buffer in the coded block order. A multiplexer circuit is configured to flush data from the first buffer in raster scan order in response to a completed set of the first type component blocks in the first buffer, and flush data from the second buffer in raster scan order in response to a completed set of the second type component blocks in the second buffer.