Codeword Layout Across Memory Blocks for Error Rate Reduction
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Solution Overview
Problem
Existing memory systems face challenges in reducing peak error rates across multiple memory blocks, which can lead to systematic dependencies and design limitations due to varying error rates in different locations within the memory array.
Innovation Solution
The method involves writing portions of a codeword in different locations across multiple memory blocks, taking into account the varying error rates of each location to mitigate peak error sources, thereby reducing overall error rates and optimizing system design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuitry is extended to cover all memory locations, then reliability improves, but device complexity and cost increase
Solution Approach 1:
The patent applies local quality by providing error correction circuitry only for specific memory locations that exhibit higher error rates, rather than uniformly across all locations. Different portions of the memory array are treated differently based on their observed error characteristics, with some locations receiving error correction resources and others not, thereby optimizing the balance between reliability and complexity.
2Device complexity
If error correction circuitry is reduced, then device complexity decreases, but reliability worsens due to uncorrectable errors
Solution Approach 1:
The patent changes the parameter of error correction allocation from a uniform approach to a variable approach based on location-specific error rates. By measuring and characterizing error rates for different portions of the memory array, the system dynamically adjusts the level of error correction provided to each location, reducing complexity where errors are rare while maintaining reliability where errors are common.
3Ease of manufacture
If memory locations with high error rates are used, then manufacturing cost decreases, but systematic dependencies increase
Solution Approach 1:
The patent changes operational parameters such as read voltages, write voltages, and refresh timings based on the specific error characteristics of each memory location. By adjusting these parameters for locations with higher error rates, the system can reliably use lower-cost memory configurations while compensating for systematic errors through parameter optimization rather than requiring uniform high-quality components throughout.
Data Source
AI summary
Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location of the second memory block can be different than the first location of the first memory block.