Variable Code Rate Codeword Mapping for SSD Storage Flexibility
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Solution Overview
Problem
Existing memory systems face limitations in efficiently managing the correspondence between physical and logical pages, leading to inflexible storage solutions that do not optimize storage capacity and throughput, particularly in solid-state drives (SSDs).
Innovation Solution
The solution involves error coding logical pages of data into codewords that can be written to physical pages of memory independently of their size, allowing for variable code rates and flexible stripe lengths, while maintaining a constant codeword size, and using a RAIN (Redundant Array of Independent NAND) component for defect protection, keeping firmware out of the performance path to enhance speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logical pages are error coded into codewords that can be written to physical pages independently of their size, then storage flexibility and adaptability are improved, but device complexity increases due to variable code rates and RAIN component management
Solution Approach 1:
The system segments data into fixed-size codewords that are independent of physical page sizes. Multiple codewords can be distributed across multiple physical pages, allowing flexible mapping between logical and physical storage layers while maintaining manageable unit sizes for encoding and decoding operations
Solution Approach 2:
The RAIN component provides defect protection functionality that works universally across different physical page sizes and configurations. The same error coding and protection mechanisms can be applied regardless of the underlying physical storage architecture, enabling a single system to handle multiple storage scenarios
2Productivity
If firmware is kept out of the performance path to enhance speed, then productivity is improved, but reliability may worsen due to reduced firmware intervention for error handling
Solution Approach 1:
Error correction codes are pre-calculated and embedded into the data structure during the write operation. The redundancy information is prepared in advance and stored alongside the data, allowing error correction to occur automatically during read operations without requiring firmware intervention, thus maintaining both high throughput and reliability
Solution Approach 2:
The error correction mechanism operates autonomously through hardware-based decoding circuits that can correct errors without firmware involvement. The system self-manages error detection and correction, freeing the firmware from performance-critical error handling tasks while maintaining data integrity
3Quantity of substance
If buffer memory is managed in codeword payload sizes rather than physical page sizes, then storage efficiency is improved, but device complexity increases due to additional mapping and management overhead
Solution Approach 1:
The system introduces a new dimension of abstraction by managing buffers in terms of codeword payloads rather than physical pages. This creates a logical buffer management layer that is independent of physical page boundaries, allowing more efficient utilization of storage capacity while the mapping between codewords and physical pages is handled by the controller
Data Source
AI summary
The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.