Coding Circuit for Out-of-Boundary 2-Bit Error Correction

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Solution Overview

Problem

Conventional 1-symbol correction Reed-Solomon (RS) codes cannot correct 2-bit errors occurring beyond one symbol boundary, and applying Bose-Chaudhuri-Hocquenghem (BCH) codes requires additional parity bits, increasing encoder and decoder circuit area.

Innovation Solution

A coding circuit that generates parity using a parity generating matrix and concatenates input data and parity to correct out-of-boundary 2-bit errors using syndromes, without increasing parity bits, by employing a decoder circuit to detect and correct 2-bit errors across two symbols.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If BCH code is applied to correct 2-bit errors beyond one symbol boundary, then error correction capability is improved, but encoder and decoder circuit area increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges RS code and BCH code into a hybrid coding scheme where RS code handles 1-symbol errors and BCH code handles out-of-boundary 2-bit errors. The syndromes from RS decoding are reused to detect and correct BCH errors, combining the strengths of both codes while avoiding redundant circuitry.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The parity generating matrix serves multiple functions: it generates parity bits for RS encoding, generates syndromes for error detection, and enables both RS and BCH error correction. This multi-functionality eliminates the need for separate processing circuits for different error types.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If additional parity bits are added for BCH code, then out-of-boundary error correction is improved, but bandwidth efficiency deteriorates

Engineering Contradiction:

Improveout-of-boundary error correctionVSAvoidbandwidth efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The parity bits are pre-calculated using the parity generating matrix during the encoding phase. These same parity bits serve dual purposes: enabling RS code generation and providing syndromes for BCH error detection and correction, eliminating the need for additional parity bits.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the interpretation and usage of the parity bits generated by the parity generating matrix. Instead of being dedicated solely to RS code, these parity bits are repurposed to also serve BCH code requirements through syndrome calculation, thereby maintaining bandwidth efficiency while achieving out-of-boundary error correction.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12407366B2Coding circuit and memory device including the same

Publication Date: 2025.09.02 SK HYNIX INC

AI summary

A coding circuit includes an encoder circuit that generates parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity, and a decoder circuit that detects and corrects an out-of-boundary 2-bit error using syndromes. The out-of-boundary 2-bit error corresponds to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, and the syndromes are generated by applying the output codeword to the parity generating matrix.