Chip-on-film package structure with multi-row upper pads
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Solution Overview
Problem
The increasing demand for higher integrated circuit density in chip-on-film (COF) package structures limits the number and pitch of leads on flexible substrates, particularly due to the constraints of chip size, lead width, and the area occupied by conductive vias, making it difficult to increase the number of bumps on the output side of the driver IC.
Innovation Solution
A COF package structure with a double-sided flexible substrate where the second upper leads are divided into groups with upper pads arranged in multiple rows within the chip mounting area, connected by conductive vias to lower leads, allowing for a significant increase in the number of leads and reducing lead pitches without occupying additional space outside the chip mounting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If leads are extended from chip mounting area through conductive vias outside the chip mounting area, then the number of leads can be increased, but the area for lead distribution is reduced
Solution Approach 1:
The patent transitions from single-sided lead arrangement to double-sided lead arrangement. Leads are extended from the chip mounting area through conductive vias to the other side of the flexible substrate, utilizing the third dimension (depth/through-thickness direction) to increase lead capacity without consuming additional planar area. This dimensional transition allows leads to be distributed on both upper and lower surfaces, effectively doubling the available lead distribution area.
2Quantity of substance
If the amount of bumps on the output side of the driver IC is increased, then the integrated circuit density is improved, but the number of leads capable of passing through the chip edge is limited
Solution Approach 1:
The patent utilizes the through-thickness dimension by extending leads through conductive vias to the other side of the flexible substrate. This allows bumps to be connected to leads on both the upper and lower surfaces of the chip, effectively doubling the lead capacity per chip edge without increasing the chip edge length or width.
Solution Approach 2:
The patent segments the lead paths into multiple groups passing through different conductive vias at different locations around the chip. This segmentation allows independent routing of lead groups, enabling increased total lead count while maintaining acceptable pitch and width constraints for each individual lead path.
3Manufacturing precision
If lead width and pitches are maintained within standard constraints, then manufacturing precision is ensured, but the number of leads that can be accommodated is limited
Solution Approach 1:
By utilizing the through-thickness dimension with conductive vias, the patent creates additional lead pathways without compromising the planar lead width and pitch dimensions. Leads on both upper and lower surfaces can maintain standard manufacturing tolerances while the overall system accommodates more leads through the vertical dimension.
Data Source
AI summary
A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.