Chip-on-Film Package with Non-Overlapping Lines for Bending Stress Relief
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Solution Overview
Problem
Chip-on-film packages in display devices are prone to wire cracking at bending areas, leading to defects and deterioration in display quality due to accumulated bending stress.
Innovation Solution
A chip-on-film package design featuring a base film with an integrated circuit chip, a first line on the upper surface overlapping the bending area, a second line on the lower surface, and a via pattern penetrating the base film to electrically couple the lines, with a common line that does not overlap the bending area, ensuring symmetrical and non-overlapping intermediate lines for stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the COF package is bent to connect the display panel and printed circuit board, then the electrical coupling between the display panel and printed circuit board is achieved, but wire cracking occurs at the bending area due to accumulated bending stress
Solution Approach 1:
The wire structure is segmented into multiple components: first wire on the upper surface, second wire on the lower surface, and intermediate wire connecting them. This segmentation distributes the bending stress across multiple segments rather than concentrating it in a single wire, preventing wire cracking while maintaining flexibility.
Solution Approach 2:
The wire structure transitions from a two-dimensional planar layout to a three-dimensional configuration by adding the intermediate wire that connects the first and second wires through via patterns. This vertical dimension provides additional stress relief paths and prevents cracking by distributing mechanical stress across multiple spatial dimensions.
2Reliability
If the first line and second line are positioned to overlap the bending area for electrical coupling, then signal transmission is enabled, but stress concentration occurs at the overlapping region
Solution Approach 1:
The intermediate line is designed with a narrower width compared to the first and second lines. This local variation in geometric properties reduces the stress concentration at the overlapping region while maintaining adequate electrical coupling. The via patterns are strategically positioned to provide stress relief points without compromising electrical connectivity.
Data Source
AI summary
A chip-on-film package includes a base film including a bending area, an integrated circuit chip at an upper surface of the base film, a first line at the upper surface of the base film and overlapping the bending area, a second line at a lower surface of the base film and overlapping the bending area, a via pattern penetrating the base film to electrically couple the first line and the second line, and a common line coupled to the first line and to the integrated circuit chip, wherein at least a portion of the first line does not overlap at least a portion of the second line in a plan view.